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1e820da3c9
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 Embedded Alley Solutions, Inc
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2009 Jiajie Chen (chenjiajie@cse.buaa.edu.cn)
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* Copyright (C) 2012 Huacai Chen (chenhc@lemote.com)
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*/
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#ifndef __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
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#define __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H
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/*
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* Override macros used in arch/mips/kernel/head.S.
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*/
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.macro kernel_entry_setup
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#ifdef CONFIG_CPU_LOONGSON3
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.set push
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.set mips64
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/* Set LPA on LOONGSON3 config3 */
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mfc0 t0, $16, 3
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or t0, (0x1 << 7)
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mtc0 t0, $16, 3
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/* Set ELPA on LOONGSON3 pagegrain */
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mfc0 t0, $5, 1
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or t0, (0x1 << 29)
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mtc0 t0, $5, 1
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#ifdef CONFIG_LOONGSON3_ENHANCEMENT
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/* Enable STFill Buffer */
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mfc0 t0, $16, 6
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or t0, 0x100
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mtc0 t0, $16, 6
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#endif
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_ehb
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.set pop
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#endif
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.endm
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/*
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* Do SMP slave processor setup.
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*/
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.macro smp_slave_setup
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#ifdef CONFIG_CPU_LOONGSON3
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.set push
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.set mips64
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/* Set LPA on LOONGSON3 config3 */
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mfc0 t0, $16, 3
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or t0, (0x1 << 7)
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mtc0 t0, $16, 3
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/* Set ELPA on LOONGSON3 pagegrain */
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mfc0 t0, $5, 1
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or t0, (0x1 << 29)
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mtc0 t0, $5, 1
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#ifdef CONFIG_LOONGSON3_ENHANCEMENT
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/* Enable STFill Buffer */
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mfc0 t0, $16, 6
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or t0, 0x100
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mtc0 t0, $16, 6
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#endif
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_ehb
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.set pop
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#endif
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.endm
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#endif /* __ASM_MACH_LOONGSON64_KERNEL_ENTRY_H */
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