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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 01:21:01 +07:00
1ec7032ad5
Some of the peripheral clocks on Tegra are derived from one of the top- level PLLs with a fixed factor. Support these clocks by implementing the ->enable() and ->disable() callbacks using the peripheral clock register banks and the ->recalc_rate() by dividing the parent rate by the fixed factor. Signed-off-by: Thierry Reding <treding@nvidia.com>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk-provider.h>
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#include "clk.h"
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static inline struct tegra_clk_periph_fixed *
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to_tegra_clk_periph_fixed(struct clk_hw *hw)
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{
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return container_of(hw, struct tegra_clk_periph_fixed, hw);
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}
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static int tegra_clk_periph_fixed_is_enabled(struct clk_hw *hw)
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{
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struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
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u32 mask = 1 << (fixed->num % 32), value;
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value = readl(fixed->base + fixed->regs->enb_reg);
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if (value & mask) {
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value = readl(fixed->base + fixed->regs->rst_reg);
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if ((value & mask) == 0)
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return 1;
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}
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return 0;
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}
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static int tegra_clk_periph_fixed_enable(struct clk_hw *hw)
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{
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struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
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u32 mask = 1 << (fixed->num % 32);
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writel(mask, fixed->base + fixed->regs->enb_set_reg);
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return 0;
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}
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static void tegra_clk_periph_fixed_disable(struct clk_hw *hw)
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{
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struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
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u32 mask = 1 << (fixed->num % 32);
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writel(mask, fixed->base + fixed->regs->enb_clr_reg);
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}
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static unsigned long
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tegra_clk_periph_fixed_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct tegra_clk_periph_fixed *fixed = to_tegra_clk_periph_fixed(hw);
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unsigned long long rate;
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rate = (unsigned long long)parent_rate * fixed->mul;
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do_div(rate, fixed->div);
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return (unsigned long)rate;
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}
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static const struct clk_ops tegra_clk_periph_fixed_ops = {
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.is_enabled = tegra_clk_periph_fixed_is_enabled,
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.enable = tegra_clk_periph_fixed_enable,
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.disable = tegra_clk_periph_fixed_disable,
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.recalc_rate = tegra_clk_periph_fixed_recalc_rate,
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};
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struct clk *tegra_clk_register_periph_fixed(const char *name,
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const char *parent,
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unsigned long flags,
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void __iomem *base,
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unsigned int mul,
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unsigned int div,
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unsigned int num)
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{
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const struct tegra_clk_periph_regs *regs;
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struct tegra_clk_periph_fixed *fixed;
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struct clk_init_data init;
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struct clk *clk;
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regs = get_reg_bank(num);
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if (!regs)
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return ERR_PTR(-EINVAL);
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fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
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if (!fixed)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.flags = flags;
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init.parent_names = parent ? &parent : NULL;
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init.num_parents = parent ? 1 : 0;
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init.ops = &tegra_clk_periph_fixed_ops;
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fixed->base = base;
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fixed->regs = regs;
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fixed->mul = mul;
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fixed->div = div;
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fixed->num = num;
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fixed->hw.init = &init;
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clk = clk_register(NULL, &fixed->hw);
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if (IS_ERR(clk))
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kfree(fixed);
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return clk;
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}
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