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d2c0bdaa93
The McBSP1 port in OMAP3 processors (I believe OMAP2 too but I don't have specifications to check it) have additional CLKR and FSR pins for McBSP1 receiver. Reset default is that receiver is using bit clock and frame sync signal from those pins but it is possible to configure to use also CLKX and FSX pins as well. In fact, other McBSP ports are doing that internally that transmitter and receiver share the CLKX and FSX. Add functionaly that machine drivers can set the CLKR and FSR sources by using the snd_soc_dai_set_sysclk. Thanks to "Aggarwal, Anuj" <anuj.aggarwal@ti.com> for reporting the issue. Signed-off-by: Jarkko Nikula <jhnikula@gmail.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> |
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| .. | ||
| ams-delta.c | ||
| Kconfig | ||
| Makefile | ||
| n810.c | ||
| omap2evm.c | ||
| omap3beagle.c | ||
| omap3evm.c | ||
| omap3pandora.c | ||
| omap-mcbsp.c | ||
| omap-mcbsp.h | ||
| omap-pcm.c | ||
| omap-pcm.h | ||
| osk5912.c | ||
| overo.c | ||
| sdp3430.c | ||
| zoom2.c | ||