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9e0e59993d
On a Thinkpad s30 (Pentium III / i440MX, Lynx3DM), running fbtest or X will crash the machine instantly, because the VRAM/framebuffer is not mapped correctly. On SM712, the framebuffer starts at the beginning of address space, but SM720's framebuffer starts at the 1 MiB offset from the beginning. However, sm712fb fails to take this into account, as a result, writing to the framebuffer will destroy all the registers and kill the system immediately. Another problem is the driver assumes 8 MiB of VRAM for SM720, but some SM720 system, such as this IBM Thinkpad, only has 4 MiB of VRAM. Fix this problem by removing the hardcoded VRAM size, adding a function to query the amount of VRAM from register MCR76 on SM720, and adding proper framebuffer offset. Please note that the memory map may have additional problems on Big-Endian system, which is not available for testing by myself. But I highly suspect that the original code is also broken on Big-Endian machines for SM720, so at least we are not making the problem worse. More, the driver also assumed SM710/SM712 has 4 MiB of VRAM, but it has a 2 MiB version as well, and used in earlier laptops, such as IBM Thinkpad 240X, the driver would probably crash on them. I've never seen one of those machines and cannot fix it, but I have documented these problems in the comments. Signed-off-by: Yifeng Li <tomli@tomli.me> Tested-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com> Cc: Teddy Wang <teddy.wang@siliconmotion.com> Cc: <stable@vger.kernel.org> # v4.4+ Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
112 lines
3.0 KiB
C
112 lines
3.0 KiB
C
/*
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* Silicon Motion SM712 frame buffer device
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*
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* Copyright (C) 2006 Silicon Motion Technology Corp.
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* Authors: Ge Wang, gewang@siliconmotion.com
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* Boyod boyod.yang@siliconmotion.com.cn
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*
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* Copyright (C) 2009 Lemote, Inc.
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* Author: Wu Zhangjin, wuzhangjin@gmail.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#define FB_ACCEL_SMI_LYNX 88
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#define SCREEN_X_RES 1024
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#define SCREEN_Y_RES 600
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#define SCREEN_BPP 16
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#define dac_reg (0x3c8)
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#define dac_val (0x3c9)
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extern void __iomem *smtc_regbaseaddress;
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#define smtc_mmiowb(dat, reg) writeb(dat, smtc_regbaseaddress + reg)
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#define smtc_mmiorb(reg) readb(smtc_regbaseaddress + reg)
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#define SIZE_SR00_SR04 (0x04 - 0x00 + 1)
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#define SIZE_SR10_SR24 (0x24 - 0x10 + 1)
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#define SIZE_SR30_SR75 (0x75 - 0x30 + 1)
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#define SIZE_SR80_SR93 (0x93 - 0x80 + 1)
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#define SIZE_SRA0_SRAF (0xAF - 0xA0 + 1)
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#define SIZE_GR00_GR08 (0x08 - 0x00 + 1)
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#define SIZE_AR00_AR14 (0x14 - 0x00 + 1)
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#define SIZE_CR00_CR18 (0x18 - 0x00 + 1)
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#define SIZE_CR30_CR4D (0x4D - 0x30 + 1)
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#define SIZE_CR90_CRA7 (0xA7 - 0x90 + 1)
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static inline void smtc_crtcw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3d4);
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smtc_mmiowb(val, 0x3d5);
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}
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static inline void smtc_grphw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3ce);
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smtc_mmiowb(val, 0x3cf);
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}
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static inline void smtc_attrw(int reg, int val)
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{
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smtc_mmiorb(0x3da);
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smtc_mmiowb(reg, 0x3c0);
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smtc_mmiorb(0x3c1);
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smtc_mmiowb(val, 0x3c0);
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}
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static inline void smtc_seqw(int reg, int val)
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{
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smtc_mmiowb(reg, 0x3c4);
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smtc_mmiowb(val, 0x3c5);
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}
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static inline unsigned int smtc_seqr(int reg)
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{
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smtc_mmiowb(reg, 0x3c4);
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return smtc_mmiorb(0x3c5);
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}
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/* The next structure holds all information relevant for a specific video mode.
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*/
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struct modeinit {
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int mmsizex;
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int mmsizey;
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int bpp;
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int hz;
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unsigned char init_misc;
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unsigned char init_sr00_sr04[SIZE_SR00_SR04];
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unsigned char init_sr10_sr24[SIZE_SR10_SR24];
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unsigned char init_sr30_sr75[SIZE_SR30_SR75];
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unsigned char init_sr80_sr93[SIZE_SR80_SR93];
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unsigned char init_sra0_sraf[SIZE_SRA0_SRAF];
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unsigned char init_gr00_gr08[SIZE_GR00_GR08];
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unsigned char init_ar00_ar14[SIZE_AR00_AR14];
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unsigned char init_cr00_cr18[SIZE_CR00_CR18];
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unsigned char init_cr30_cr4d[SIZE_CR30_CR4D];
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unsigned char init_cr90_cra7[SIZE_CR90_CRA7];
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};
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#ifdef __BIG_ENDIAN
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#define pal_rgb(r, g, b, val) (((r & 0xf800) >> 8) | \
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((g & 0xe000) >> 13) | \
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((g & 0x1c00) << 3) | \
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((b & 0xf800) >> 3))
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#define big_addr 0x800000
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#define mmio_addr 0x00800000
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#define seqw17() smtc_seqw(0x17, 0x30)
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#define big_pixel_depth(p, d) {if (p == 24) {p = 32; d = 32; } }
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#define big_swap(p) ((p & 0xff00ff00 >> 8) | (p & 0x00ff00ff << 8))
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#else
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#define pal_rgb(r, g, b, val) val
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#define big_addr 0
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#define mmio_addr 0x00c00000
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#define seqw17() do { } while (0)
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#define big_pixel_depth(p, d) do { } while (0)
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#define big_swap(p) p
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#endif
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