mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 16:26:57 +07:00
1bbe0ecc2a
This patch adds support for initializing the MACsec engine found within some Microsemi PHYs. The engine is initialized in a passthrough mode and does not modify any incoming or outgoing packet. But thanks to this it now can be configured to perform MACsec transformations on packets, which will be supported by a future patch. The MACsec read and write functions are wrapped into two versions: one called during the init phase, and the other one later on. This is because the init functions in the Microsemi PHY driver are called while the MDIO bus lock is taken. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Signed-off-by: David S. Miller <davem@davemloft.net>
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (C) 2019 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_FC_BUFFER_H_
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#define _MSCC_OCELOT_FC_BUFFER_H_
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#define MSCC_FCBUF_ENA_CFG 0x00
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#define MSCC_FCBUF_MODE_CFG 0x01
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG 0x02
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#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG 0x03
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#define MSCC_FCBUF_TX_DATA_QUEUE_CFG 0x04
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#define MSCC_FCBUF_RX_DATA_QUEUE_CFG 0x05
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#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG 0x06
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#define MSCC_FCBUF_FC_READ_THRESH_CFG 0x07
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#define MSCC_FCBUF_TX_FRM_GAP_COMP 0x08
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#define MSCC_FCBUF_ENA_CFG_TX_ENA BIT(0)
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#define MSCC_FCBUF_ENA_CFG_RX_ENA BIT(4)
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#define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR BIT(4)
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#define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA BIT(8)
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#define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA BIT(12)
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#define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA BIT(16)
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#define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA BIT(20)
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#define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA BIT(24)
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#define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x) (x)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x) ((x) << 16)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M GENMASK(19, 16)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x) ((x) << 20)
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#define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M GENMASK(31, 20)
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#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x) (x)
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#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M GENMASK(15, 0)
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#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x) ((x) << 16)
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#define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M GENMASK(31, 16)
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#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x) (x)
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#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
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#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x) ((x) << 16)
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#define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
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#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x) (x)
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#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M GENMASK(15, 0)
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#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x) ((x) << 16)
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#define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M GENMASK(31, 16)
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#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x) (x)
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#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M GENMASK(15, 0)
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#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x) ((x) << 16)
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#define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16)
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#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x) (x)
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#define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M GENMASK(15, 0)
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#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x) ((x) << 16)
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#define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M GENMASK(31, 16)
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#endif
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