mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 09:10:51 +07:00
8546dc1d4b
Pull ARM updates from Russell King:
"The major items included in here are:
- MCPM, multi-cluster power management, part of the infrastructure
required for ARMs big.LITTLE support.
- A rework of the ARM KVM code to allow re-use by ARM64.
- Error handling cleanups of the IS_ERR_OR_NULL() madness and fixes
of that stuff for arch/arm
- Preparatory patches for Cortex-M3 support from Uwe Kleine-König.
There is also a set of three patches in here from Hugh/Catalin to
address freeing of inappropriate page tables on LPAE. You already
have these from akpm, but they were already part of my tree at the
time he sent them, so unfortunately they'll end up with duplicate
commits"
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits)
ARM: EXYNOS: remove unnecessary use of IS_ERR_VALUE()
ARM: IMX: remove unnecessary use of IS_ERR_VALUE()
ARM: OMAP: use consistent error checking
ARM: cleanup: OMAP hwmod error checking
ARM: 7709/1: mcpm: Add explicit AFLAGS to support v6/v7 multiplatform kernels
ARM: 7700/2: Make cpu_init() notrace
ARM: 7702/1: Set the page table freeing ceiling to TASK_SIZE
ARM: 7701/1: mm: Allow arch code to control the user page table ceiling
ARM: 7703/1: Disable preemption in broadcast_tlb*_a15_erratum()
ARM: mcpm: provide an interface to set the SMP ops at run time
ARM: mcpm: generic SMP secondary bringup and hotplug support
ARM: mcpm_head.S: vlock-based first man election
ARM: mcpm: Add baremetal voting mutexes
ARM: mcpm: introduce helpers for platform coherency exit/setup
ARM: mcpm: introduce the CPU/cluster power API
ARM: multi-cluster PM: secondary kernel entry code
ARM: cacheflush: add synchronization helpers for mixed cache state accesses
ARM: cpu hotplug: remove majority of cache flushing from platforms
ARM: smp: flush L1 cache in cpu_die()
ARM: tegra: remove tegra specific cpu_disable()
...
130 lines
3.3 KiB
C
130 lines
3.3 KiB
C
/*
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* SMP support for R-Mobile / SH-Mobile - sh73a0 portion
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Takashi Yoshii
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/common.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <mach/sh73a0.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#define WUPCR IOMEM(0xe6151010)
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#define SRESCR IOMEM(0xe6151018)
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#define PSTR IOMEM(0xe6151040)
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#define SBAR IOMEM(0xe6180020)
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#define APARMBAREA IOMEM(0xe6f10020)
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#define PSTR_SHUTDOWN_MODE 3
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#define SH73A0_SCU_BASE 0xf0000000
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
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void __init sh73a0_register_twd(void)
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{
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twd_local_timer_register(&twd_local_timer);
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}
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#endif
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static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, WUPCR); /* wake up */
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else
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__raw_writel(1 << cpu, SRESCR); /* reset */
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return 0;
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}
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static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(shmobile_scu_base);
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/* Map the reset vector (in headsmp-scu.S) */
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__raw_writel(0, APARMBAREA); /* 4k */
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__raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
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/* enable cache coherency on booting CPU */
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scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
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}
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static void __init sh73a0_smp_init_cpus(void)
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{
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/* setup sh73a0 specific SCU base */
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shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
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shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
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}
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#ifdef CONFIG_HOTPLUG_CPU
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static int sh73a0_cpu_kill(unsigned int cpu)
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{
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int k;
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u32 pstr;
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/*
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* wait until the power status register confirms the shutdown of the
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* offline target
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*/
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for (k = 0; k < 1000; k++) {
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pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3;
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if (pstr == PSTR_SHUTDOWN_MODE)
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return 1;
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mdelay(1);
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}
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return 0;
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}
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static void sh73a0_cpu_die(unsigned int cpu)
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{
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/* Set power off mode. This takes the CPU out of the MP cluster */
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scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
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/* Enter shutdown mode */
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cpu_do_idle();
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}
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static int sh73a0_cpu_disable(unsigned int cpu)
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{
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return 0; /* CPU0 and CPU1 supported */
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}
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#endif /* CONFIG_HOTPLUG_CPU */
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struct smp_operations sh73a0_smp_ops __initdata = {
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.smp_init_cpus = sh73a0_smp_init_cpus,
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.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
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.smp_boot_secondary = sh73a0_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = sh73a0_cpu_kill,
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.cpu_die = sh73a0_cpu_die,
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.cpu_disable = sh73a0_cpu_disable,
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#endif
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};
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