Heiko Stuebner 9def7ccfe8 ARM: rockchip: add support smp for rk3036 ... The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control. So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Xing Zheng <zhengxing@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org>		2015-11-19 05:53:35 +01:00
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core.h	ARM: v7 setup function should invalidate L1 cache	2015-06-01 11:30:26 +01:00
headsmp.S	ARM: v7 setup function should invalidate L1 cache	2015-06-01 11:30:26 +01:00
Kconfig	ARM: rockchip: force built-in regulator support for PM	2015-02-18 12:20:30 +01:00
Makefile	ARM: rockchip: add suspend and resume for RK3288	2014-12-31 16:16:50 +01:00
platsmp.c	ARM: rockchip: add support smp for rk3036	2015-11-19 05:53:35 +01:00
pm.c	ARM: rockchip: pm: Fix PTR_ERR() argument	2015-08-24 12:39:14 +02:00
pm.h	ARM: rockchip: enable PMU_GPIOINT_WAKEUP_EN when entering shallow suspend	2015-08-06 13:05:14 +02:00
rockchip.c	clocksource: cosmetic: Drop OF 'dependency' from symbols	2015-10-01 02:18:39 +02:00
sleep.S	ARM: rockchip: add suspend and resume for RK3288	2014-12-31 16:16:50 +01:00