mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 15:47:05 +07:00
9710ee14be
- Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* EMMA Mobile EV2 common clock framework support
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*
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* Copyright (C) 2013 Takashi Yoshii <takashi.yoshii.ze@renesas.com>
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* Copyright (C) 2012 Magnus Damm
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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/* EMEV2 SMU registers */
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#define USIAU0_RSTCTRL 0x094
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#define USIBU1_RSTCTRL 0x0ac
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#define USIBU2_RSTCTRL 0x0b0
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#define USIBU3_RSTCTRL 0x0b4
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#define IIC0_RSTCTRL 0x0dc
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#define IIC1_RSTCTRL 0x0e0
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#define STI_RSTCTRL 0x124
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#define STI_CLKSEL 0x688
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static DEFINE_SPINLOCK(lock);
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/* not pretty, but hey */
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static void __iomem *smu_base;
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static void __init emev2_smu_write(unsigned long value, int offs)
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{
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BUG_ON(!smu_base || (offs >= PAGE_SIZE));
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writel_relaxed(value, smu_base + offs);
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}
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static const struct of_device_id smu_id[] __initconst = {
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{ .compatible = "renesas,emev2-smu", },
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{},
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};
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static void __init emev2_smu_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, smu_id);
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BUG_ON(!np);
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smu_base = of_iomap(np, 0);
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BUG_ON(!smu_base);
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of_node_put(np);
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/* setup STI timer to run on 32.768 kHz and deassert reset */
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emev2_smu_write(0, STI_CLKSEL);
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emev2_smu_write(1, STI_RSTCTRL);
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/* deassert reset for UART0->UART3 */
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emev2_smu_write(2, USIAU0_RSTCTRL);
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emev2_smu_write(2, USIBU1_RSTCTRL);
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emev2_smu_write(2, USIBU2_RSTCTRL);
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emev2_smu_write(2, USIBU3_RSTCTRL);
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/* deassert reset for IIC0->IIC1 */
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emev2_smu_write(1, IIC0_RSTCTRL);
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emev2_smu_write(1, IIC1_RSTCTRL);
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}
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static void __init emev2_smu_clkdiv_init(struct device_node *np)
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{
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u32 reg[2];
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struct clk *clk;
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const char *parent_name = of_clk_get_parent_name(np, 0);
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if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
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return;
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if (!smu_base)
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emev2_smu_init();
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clk = clk_register_divider(NULL, np->name, parent_name, 0,
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smu_base + reg[0], reg[1], 8, 0, &lock);
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, np->full_name, NULL);
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pr_debug("## %s %pOFn %p\n", __func__, np, clk);
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}
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CLK_OF_DECLARE(emev2_smu_clkdiv, "renesas,emev2-smu-clkdiv",
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emev2_smu_clkdiv_init);
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static void __init emev2_smu_gclk_init(struct device_node *np)
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{
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u32 reg[2];
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struct clk *clk;
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const char *parent_name = of_clk_get_parent_name(np, 0);
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if (WARN_ON(of_property_read_u32_array(np, "reg", reg, 2)))
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return;
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if (!smu_base)
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emev2_smu_init();
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clk = clk_register_gate(NULL, np->name, parent_name, 0,
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smu_base + reg[0], reg[1], 0, &lock);
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of_clk_add_provider(np, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, np->full_name, NULL);
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pr_debug("## %s %pOFn %p\n", __func__, np, clk);
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}
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CLK_OF_DECLARE(emev2_smu_gclk, "renesas,emev2-smu-gclk", emev2_smu_gclk_init);
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