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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9dcd1f26b9
As the PHY interface installed on the V3MSK board provides TX and RX channels delays, make the "phy-mode" property a board-specific one, meant to override the one specified in the SoC DTSI. Follow up patches will reset the r8a77970 SoC DTSI to use "rgmii" mode and let the board file override that. Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
57 lines
1000 B
Plaintext
57 lines
1000 B
Plaintext
/*
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* Device Tree Source for the V3M Starter Kit board
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*
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* Copyright (C) 2017 Renesas Electronics Corp.
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* Copyright (C) 2017 Cogent Embedded, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/dts-v1/;
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#include "r8a77970.dtsi"
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/ {
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model = "Renesas V3M Starter Kit board";
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compatible = "renesas,v3msk", "renesas,r8a77970";
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aliases {
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serial0 = &scif0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x38000000>;
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};
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};
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&avb {
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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phy0: ethernet-phy@0 {
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rxc-skew-ps = <1500>;
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reg = <0>;
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};
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};
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&extal_clk {
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clock-frequency = <16666666>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&scif0 {
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status = "okay";
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};
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