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f40739faba
Commit 8c8a777 (ARM: OMAP2+: Add function to read GPMC settings from device-tree) added a device-tree property "gpmc,device-nand" to indicate is the GPMC child device is NAND. This commit should have updated the GPMC NAND documentation (Documentation/devicetree/bindings/mtd/gpmc-nand.txt) to list the property "gpmc,device-nand" as a required property and also updated the example. However, this property is redundant and not needed because the GPMC child device node for NAND is called "nand". Therefore, remove this property. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
146 lines
3.3 KiB
C
146 lines
3.3 KiB
C
/*
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* gpmc-nand.c
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*
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* Copyright (C) 2009 Texas Instruments
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* Vimal Singh <vimalsingh@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/mtd/nand.h>
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#include <linux/platform_data/mtd-nand-omap2.h>
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#include <asm/mach/flash.h>
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#include "gpmc.h"
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#include "soc.h"
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#include "gpmc-nand.h"
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/* minimum size for IO mapping */
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#define NAND_IO_SIZE 4
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static struct resource gpmc_nand_resource[] = {
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{
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.flags = IORESOURCE_MEM,
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},
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{
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.flags = IORESOURCE_IRQ,
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},
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device gpmc_nand_device = {
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.name = "omap2-nand",
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.id = 0,
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.num_resources = ARRAY_SIZE(gpmc_nand_resource),
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.resource = gpmc_nand_resource,
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};
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static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
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{
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/* support only OMAP3 class */
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if (!cpu_is_omap34xx() && !soc_is_am33xx()) {
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pr_err("BCH ecc is not supported on this CPU\n");
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return 0;
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}
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/*
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* For now, assume 4-bit mode is only supported on OMAP3630 ES1.x, x>=1
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* and AM33xx derivates. Other chips may be added if confirmed to work.
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*/
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if ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) &&
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(!cpu_is_omap3630() || (GET_OMAP_REVISION() == 0)) &&
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(!soc_is_am33xx())) {
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pr_err("BCH 4-bit mode is not supported on this CPU\n");
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return 0;
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}
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return 1;
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}
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int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
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struct gpmc_timings *gpmc_t)
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{
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int err = 0;
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struct gpmc_settings s;
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struct device *dev = &gpmc_nand_device.dev;
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memset(&s, 0, sizeof(struct gpmc_settings));
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gpmc_nand_device.dev.platform_data = gpmc_nand_data;
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err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
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(unsigned long *)&gpmc_nand_resource[0].start);
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if (err < 0) {
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dev_err(dev, "Cannot request GPMC CS %d, error %d\n",
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gpmc_nand_data->cs, err);
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return err;
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}
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gpmc_nand_resource[0].end = gpmc_nand_resource[0].start +
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NAND_IO_SIZE - 1;
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gpmc_nand_resource[1].start =
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gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE);
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gpmc_nand_resource[2].start =
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gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
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if (gpmc_t) {
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err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
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if (err < 0) {
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dev_err(dev, "Unable to set gpmc timings: %d\n", err);
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return err;
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}
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if (gpmc_nand_data->of_node) {
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gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
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} else {
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/* Enable RD PIN Monitoring Reg */
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if (gpmc_nand_data->dev_ready) {
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s.wait_on_read = true;
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s.wait_on_write = true;
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}
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}
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s.device_nand = true;
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if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
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s.device_width = GPMC_DEVWIDTH_16BIT;
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else
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s.device_width = GPMC_DEVWIDTH_8BIT;
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err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s);
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if (err < 0)
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goto out_free_cs;
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err = gpmc_configure(GPMC_CONFIG_WP, 0);
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if (err < 0)
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goto out_free_cs;
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}
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gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs);
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if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt))
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return -EINVAL;
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err = platform_device_register(&gpmc_nand_device);
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if (err < 0) {
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dev_err(dev, "Unable to register NAND device\n");
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goto out_free_cs;
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}
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return 0;
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out_free_cs:
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gpmc_cs_free(gpmc_nand_data->cs);
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return err;
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}
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