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a93d8a1cea
omap36xx_pwrdn_clk_enable_with_hsdiv_restore expects the parent hw of the clock to be a clk_hw_omap. However, looking at cclock3xxx_data.c, all concerned clock have parent defined as clk_divider. Fix the function to use clk_divider. Tested with 3.9 on dm3730. Signed-off-by: Jean-Philippe François <jp.francois@cynove.com> Cc: NeilBrown <neilb@suse.de> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Paul Walmsley <paul@pwsan.com>
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* OMAP36xx-specific clkops
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*
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* Mike Turquette
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* Vijaykumar GN
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* Paul Walmsley
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
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* Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include "clock.h"
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#include "clock36xx.h"
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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/**
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* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
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* from HSDivider PWRDN problem Implements Errata ID: i556.
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* @clk: DPLL output struct clk
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*
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* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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* valueafter their respective PWRDN bits are set. Any dummy write
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* (Any other value different from the Read value) to the
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* corresponding CM_CLKSEL register will refresh the dividers.
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*/
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int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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struct clk_divider *parent;
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struct clk_hw *parent_hw;
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u32 dummy_v, orig_v;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
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parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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orig_v = __raw_readl(parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << parent->shift);
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__raw_writel(dummy_v, parent->reg);
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/* Write the original divider */
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__raw_writel(orig_v, parent->reg);
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}
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return ret;
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}
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