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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ab8c609356
* pci/spdx: PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate PCI: Add SPDX GPL-2.0 when no license was specified
457 lines
11 KiB
C
457 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Texas Instruments Keystone SoCs
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*
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* Copyright (C) 2013-2014 Texas Instruments., Ltd.
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* http://www.ti.com
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*
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* Author: Murali Karicheri <m-karicheri2@ti.com>
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* Implementation based on pci-exynos.c and pcie-designware.c
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*/
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#include <linux/irqchip/chained_irq.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/of_irq.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include "pcie-designware.h"
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#include "pci-keystone.h"
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#define DRIVER_NAME "keystone-pcie"
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/* DEV_STAT_CTRL */
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#define PCIE_CAP_BASE 0x70
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/* PCIE controller device IDs */
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#define PCIE_RC_K2HK 0xb008
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#define PCIE_RC_K2E 0xb009
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#define PCIE_RC_K2L 0xb00a
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#define to_keystone_pcie(x) dev_get_drvdata((x)->dev)
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static void quirk_limit_mrrs(struct pci_dev *dev)
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{
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struct pci_bus *bus = dev->bus;
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struct pci_dev *bridge = bus->self;
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static const struct pci_device_id rc_pci_devids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
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.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
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{ 0, },
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};
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if (pci_is_root_bus(bus))
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return;
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/* look for the host bridge */
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while (!pci_is_root_bus(bus)) {
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bridge = bus->self;
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bus = bus->parent;
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}
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if (bridge) {
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/*
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* Keystone PCI controller has a h/w limitation of
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* 256 bytes maximum read request size. It can't handle
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* anything higher than this. So force this limit on
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* all downstream devices.
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*/
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if (pci_match_id(rc_pci_devids, bridge)) {
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if (pcie_get_readrq(dev) > 256) {
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dev_info(&dev->dev, "limiting MRRS to 256\n");
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pcie_set_readrq(dev, 256);
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}
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}
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}
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}
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
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static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = pci->dev;
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unsigned int retries;
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dw_pcie_setup_rc(pp);
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if (dw_pcie_link_up(pci)) {
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dev_err(dev, "Link already up\n");
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return 0;
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}
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/* check if the link is up or not */
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for (retries = 0; retries < 5; retries++) {
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ks_dw_pcie_initiate_link_train(ks_pcie);
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if (!dw_pcie_wait_for_link(pci))
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return 0;
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}
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dev_err(dev, "phy link never came up\n");
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return -ETIMEDOUT;
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}
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static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
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u32 offset = irq - ks_pcie->msi_host_irqs[0];
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struct dw_pcie *pci = ks_pcie->pci;
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struct device *dev = pci->dev;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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dev_dbg(dev, "%s, irq %d\n", __func__, irq);
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/*
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* The chained irq handler installation would have replaced normal
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* interrupt driver handler so we need to take care of mask/unmask and
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* ack operation.
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*/
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chained_irq_enter(chip, desc);
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ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
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chained_irq_exit(chip, desc);
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}
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/**
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* ks_pcie_legacy_irq_handler() - Handle legacy interrupt
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* @irq: IRQ line for legacy interrupts
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* @desc: Pointer to irq descriptor
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*
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* Traverse through pending legacy interrupts and invoke handler for each. Also
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* takes care of interrupt controller level mask/ack operation.
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*/
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static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
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{
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unsigned int irq = irq_desc_get_irq(desc);
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struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
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struct dw_pcie *pci = ks_pcie->pci;
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struct device *dev = pci->dev;
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u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
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struct irq_chip *chip = irq_desc_get_chip(desc);
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dev_dbg(dev, ": Handling legacy irq %d\n", irq);
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/*
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* The chained irq handler installation would have replaced normal
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* interrupt driver handler so we need to take care of mask/unmask and
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* ack operation.
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*/
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chained_irq_enter(chip, desc);
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ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
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chained_irq_exit(chip, desc);
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}
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static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
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char *controller, int *num_irqs)
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{
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int temp, max_host_irqs, legacy = 1, *host_irqs;
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struct device *dev = ks_pcie->pci->dev;
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struct device_node *np_pcie = dev->of_node, **np_temp;
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if (!strcmp(controller, "msi-interrupt-controller"))
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legacy = 0;
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if (legacy) {
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np_temp = &ks_pcie->legacy_intc_np;
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max_host_irqs = PCI_NUM_INTX;
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host_irqs = &ks_pcie->legacy_host_irqs[0];
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} else {
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np_temp = &ks_pcie->msi_intc_np;
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max_host_irqs = MAX_MSI_HOST_IRQS;
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host_irqs = &ks_pcie->msi_host_irqs[0];
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}
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/* interrupt controller is in a child node */
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*np_temp = of_get_child_by_name(np_pcie, controller);
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if (!(*np_temp)) {
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dev_err(dev, "Node for %s is absent\n", controller);
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return -EINVAL;
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}
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temp = of_irq_count(*np_temp);
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if (!temp) {
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dev_err(dev, "No IRQ entries in %s\n", controller);
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of_node_put(*np_temp);
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return -EINVAL;
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}
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if (temp > max_host_irqs)
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dev_warn(dev, "Too many %s interrupts defined %u\n",
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(legacy ? "legacy" : "MSI"), temp);
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/*
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* support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
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* 7 (MSI)
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*/
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for (temp = 0; temp < max_host_irqs; temp++) {
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host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
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if (!host_irqs[temp])
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break;
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}
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of_node_put(*np_temp);
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if (temp) {
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*num_irqs = temp;
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return 0;
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}
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return -EINVAL;
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}
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static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
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{
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int i;
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/* Legacy IRQ */
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for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
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irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
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ks_pcie_legacy_irq_handler,
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ks_pcie);
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}
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ks_dw_pcie_enable_legacy_irqs(ks_pcie);
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/* MSI IRQ */
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
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irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
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ks_pcie_msi_irq_handler,
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ks_pcie);
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}
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}
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if (ks_pcie->error_irq > 0)
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ks_dw_pcie_enable_error_irq(ks_pcie);
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}
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/*
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* When a PCI device does not exist during config cycles, keystone host gets a
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* bus error instead of returning 0xffffffff. This handler always returns 0
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* for this kind of faults.
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*/
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static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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unsigned long instr = *(unsigned long *) instruction_pointer(regs);
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if ((instr & 0x0e100090) == 0x00100090) {
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int reg = (instr >> 12) & 15;
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regs->uregs[reg] = -1;
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regs->ARM_pc += 4;
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}
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return 0;
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}
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static int __init ks_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
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u32 val;
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ks_pcie_establish_link(ks_pcie);
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ks_dw_pcie_setup_rc_app_regs(ks_pcie);
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ks_pcie_setup_interrupts(ks_pcie);
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writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
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pci->dbi_base + PCI_IO_BASE);
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/* update the Vendor ID */
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writew(ks_pcie->device_id, pci->dbi_base + PCI_DEVICE_ID);
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/* update the DEV_STAT_CTRL to publish right mrrs */
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val = readl(pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
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val &= ~PCI_EXP_DEVCTL_READRQ;
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/* set the mrrs to 256 bytes */
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val |= BIT(12);
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writel(val, pci->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
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/*
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* PCIe access errors that result into OCP errors are caught by ARM as
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* "External aborts"
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*/
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hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
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"Asynchronous external abort");
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return 0;
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}
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static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
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.rd_other_conf = ks_dw_pcie_rd_other_conf,
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.wr_other_conf = ks_dw_pcie_wr_other_conf,
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.host_init = ks_pcie_host_init,
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.msi_set_irq = ks_dw_pcie_msi_set_irq,
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.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
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.get_msi_addr = ks_dw_pcie_get_msi_addr,
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.msi_host_init = ks_dw_pcie_msi_host_init,
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.scan_bus = ks_dw_pcie_v3_65_scan_bus,
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};
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static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
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{
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struct keystone_pcie *ks_pcie = priv;
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return ks_dw_pcie_handle_error_irq(ks_pcie);
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}
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static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = ks_pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = &pdev->dev;
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int ret;
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ret = ks_pcie_get_irq_controller_info(ks_pcie,
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"legacy-interrupt-controller",
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&ks_pcie->num_legacy_host_irqs);
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_PCI_MSI)) {
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ret = ks_pcie_get_irq_controller_info(ks_pcie,
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"msi-interrupt-controller",
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&ks_pcie->num_msi_host_irqs);
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if (ret)
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return ret;
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}
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/*
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* Index 0 is the platform interrupt for error interrupt
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* from RC. This is optional.
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*/
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ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
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if (ks_pcie->error_irq <= 0)
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dev_info(dev, "no error IRQ defined\n");
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else {
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ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
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IRQF_SHARED, "pcie-error-irq", ks_pcie);
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if (ret < 0) {
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dev_err(dev, "failed to request error IRQ %d\n",
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ks_pcie->error_irq);
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return ret;
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}
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}
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pp->root_bus_nr = -1;
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pp->ops = &keystone_pcie_host_ops;
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ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
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if (ret) {
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dev_err(dev, "failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static const struct of_device_id ks_pcie_of_match[] = {
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{
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.type = "pci",
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.compatible = "ti,keystone-pcie",
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},
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{ },
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};
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = ks_dw_pcie_link_up,
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};
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static int __exit ks_pcie_remove(struct platform_device *pdev)
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{
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struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
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clk_disable_unprepare(ks_pcie->clk);
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return 0;
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}
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static int __init ks_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie *pci;
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struct keystone_pcie *ks_pcie;
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struct resource *res;
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void __iomem *reg_p;
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struct phy *phy;
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int ret;
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ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL);
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if (!ks_pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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ks_pcie->pci = pci;
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/* initialize SerDes Phy if present */
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phy = devm_phy_get(dev, "pcie-phy");
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if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
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return PTR_ERR(phy);
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if (!IS_ERR_OR_NULL(phy)) {
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ret = phy_init(phy);
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if (ret < 0)
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return ret;
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}
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/* index 2 is to read PCI DEVICE_ID */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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reg_p = devm_ioremap_resource(dev, res);
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if (IS_ERR(reg_p))
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return PTR_ERR(reg_p);
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ks_pcie->device_id = readl(reg_p) >> 16;
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devm_iounmap(dev, reg_p);
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devm_release_mem_region(dev, res->start, resource_size(res));
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ks_pcie->np = dev->of_node;
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platform_set_drvdata(pdev, ks_pcie);
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ks_pcie->clk = devm_clk_get(dev, "pcie");
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if (IS_ERR(ks_pcie->clk)) {
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dev_err(dev, "Failed to get pcie rc clock\n");
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return PTR_ERR(ks_pcie->clk);
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}
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ret = clk_prepare_enable(ks_pcie->clk);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, ks_pcie);
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ret = ks_add_pcie_port(ks_pcie, pdev);
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if (ret < 0)
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goto fail_clk;
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return 0;
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fail_clk:
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clk_disable_unprepare(ks_pcie->clk);
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return ret;
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}
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static struct platform_driver ks_pcie_driver __refdata = {
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.probe = ks_pcie_probe,
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.remove = __exit_p(ks_pcie_remove),
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.driver = {
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.name = "keystone-pcie",
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.of_match_table = of_match_ptr(ks_pcie_of_match),
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},
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};
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builtin_platform_driver(ks_pcie_driver);
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