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834da19705
The J-Core cpu has, as an ISA extension, an atomic compare-and-swap instruction cas.l which applications need to use (instead the imask or gusa atomic models, which are fundamentally limited to UP) for synchronization in order to be compatible with SMP systems. Provide a hwcap flag so that it's possible to do runtime selection and support both. Signed-off-by: Rich Felker <dalias@libc.org>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* arch/sh/kernel/cpu/sh2/probe.c
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*
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* CPU Subtype Probing for SH-2.
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*
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* Copyright (C) 2002 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/of_fdt.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#if defined(CONFIG_CPU_J2)
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extern u32 __iomem *j2_ccr_base;
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static int __init scan_cache(unsigned long node, const char *uname,
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int depth, void *data)
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{
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if (!of_flat_dt_is_compatible(node, "jcore,cache"))
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return 0;
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j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node);
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return 1;
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}
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#endif
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void __ref cpu_probe(void)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7619)
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boot_cpu_data.type = CPU_SH7619;
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.dcache.way_incr = (1<<12);
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boot_cpu_data.dcache.sets = 256;
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boot_cpu_data.dcache.entry_shift = 4;
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boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
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boot_cpu_data.dcache.flags = 0;
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#endif
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#if defined(CONFIG_CPU_J2)
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unsigned cpu = hard_smp_processor_id();
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if (cpu == 0) of_scan_flat_dt(scan_cache, NULL);
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if (j2_ccr_base) __raw_writel(0x80000303, j2_ccr_base + 4*cpu);
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if (cpu != 0) return;
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boot_cpu_data.type = CPU_J2;
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/* These defaults are appropriate for the original/current
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* J2 cache. Once there is a proper framework for getting cache
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* info from device tree, we should switch to that. */
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boot_cpu_data.dcache.ways = 1;
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boot_cpu_data.dcache.sets = 256;
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boot_cpu_data.dcache.entry_shift = 5;
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boot_cpu_data.dcache.linesz = 32;
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boot_cpu_data.dcache.flags = 0;
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boot_cpu_data.flags |= CPU_HAS_CAS_L;
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#else
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/*
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* SH-2 doesn't have separate caches
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*/
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boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
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#endif
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boot_cpu_data.icache = boot_cpu_data.dcache;
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boot_cpu_data.family = CPU_FAMILY_SH2;
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}
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