mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 12:26:40 +07:00
c51179fb0c
Follow up to 4732efbeb9 - uml must just reuse
as-is the backing architecture support. There is a micro-fixup is needed for the
included file, which won't affect i386 behaviour at all.
I've not tested compilation on x86_64, only on x86, but the code is almost the
same except the culprit test, so everything should be ok on x86_64 too.
Cc: Jakub Jelinek <jakub@redhat.com>
Signed-off-by: Paolo 'Blaisorblade' Giarrusso <blaisorblade@yahoo.it>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
#ifndef _ASM_FUTEX_H
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#define _ASM_FUTEX_H
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#ifdef __KERNEL__
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#include <linux/futex.h>
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#include <asm/errno.h>
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#include <asm/system.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#define __futex_atomic_op1(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile ( \
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"1: " insn "\n" \
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"2: .section .fixup,\"ax\"\n\
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3: mov %3, %1\n\
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jmp 2b\n\
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.previous\n\
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.section __ex_table,\"a\"\n\
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.align 8\n\
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.long 1b,3b\n\
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.previous" \
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: "=r" (oldval), "=r" (ret), "=m" (*uaddr) \
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: "i" (-EFAULT), "m" (*uaddr), "0" (oparg), "1" (0))
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#define __futex_atomic_op2(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile ( \
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"1: movl %2, %0\n\
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movl %0, %3\n" \
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insn "\n" \
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"2: " LOCK_PREFIX "cmpxchgl %3, %2\n\
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jnz 1b\n\
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3: .section .fixup,\"ax\"\n\
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4: mov %5, %1\n\
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jmp 3b\n\
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.previous\n\
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.section __ex_table,\"a\"\n\
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.align 8\n\
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.long 1b,4b,2b,4b\n\
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.previous" \
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: "=&a" (oldval), "=&r" (ret), "=m" (*uaddr), \
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"=&r" (tem) \
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: "r" (oparg), "i" (-EFAULT), "m" (*uaddr), "1" (0))
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static inline int
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futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
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{
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int op = (encoded_op >> 28) & 7;
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int cmp = (encoded_op >> 24) & 15;
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int oparg = (encoded_op << 8) >> 20;
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int cmparg = (encoded_op << 20) >> 20;
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int oldval = 0, ret, tem;
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
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oparg = 1 << oparg;
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if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
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return -EFAULT;
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inc_preempt_count();
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if (op == FUTEX_OP_SET)
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__futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
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else {
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#if !defined(CONFIG_X86_BSWAP) && !defined(CONFIG_UML)
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if (boot_cpu_data.x86 == 3)
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ret = -ENOSYS;
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else
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#endif
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switch (op) {
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case FUTEX_OP_ADD:
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__futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret,
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oldval, uaddr, oparg);
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break;
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case FUTEX_OP_OR:
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__futex_atomic_op2("orl %4, %3", ret, oldval, uaddr,
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oparg);
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break;
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case FUTEX_OP_ANDN:
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__futex_atomic_op2("andl %4, %3", ret, oldval, uaddr,
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~oparg);
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break;
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case FUTEX_OP_XOR:
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__futex_atomic_op2("xorl %4, %3", ret, oldval, uaddr,
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oparg);
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break;
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default:
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ret = -ENOSYS;
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}
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}
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dec_preempt_count();
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if (!ret) {
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switch (cmp) {
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case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
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case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
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case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
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case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
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case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
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case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
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default: ret = -ENOSYS;
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}
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}
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return ret;
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}
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#endif
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#endif
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