mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 16:26:43 +07:00
debd90749b
The FIR coefficients present in kernel are being updated to new coefficients consisting of 24 coefficient tables, with 12 each for 3 tap and 5 tap scenario, which are chosen on the basis of DISPC up/downsampling filters M value. M is the inverse of low pass cut off frequency of the sampling filter. For vertical scaling 3 tap or 5 tap tables are used based on the clock rate and width of the line buffer whereas in OMAP2 3 tap is always used. For horizontal scaling however 5 tap tables are always used. New coefficients and the corresponding logic have been tested on OMAP2, OMAP3 and OMAP4. Horizontal and vertical scaling worked fine except for some 3 tap vs 5 tap issue during vertical upscaling and clock failing issues which is acknowledged in the next patch. Vertical upscaling was found to perform better under 5 taps. The 24 coefficient tables have been moved to another file dispc_coefs.c for proper maintainance. This code is written based on code written by Lajos Molnar <lajos@ti.com> in Android Kernel for scaling. Lajos Molnar <lajos@ti.com> had fine tuned the FIR coefficient selection process and reduced outliness and blockiness around images when upscaling more than 2 times. Signed-off-by: Chandrabhanu Mahapatra <cmahapatra@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
760 lines
15 KiB
C
760 lines
15 KiB
C
/*
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* linux/drivers/video/omap2/dss/dispc.h
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*
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* Copyright (C) 2011 Texas Instruments
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* Author: Archit Taneja <archit@ti.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DISPC_REG_H
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#define __OMAP2_DISPC_REG_H
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/* DISPC common registers */
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#define DISPC_REVISION 0x0000
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#define DISPC_SYSCONFIG 0x0010
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#define DISPC_SYSSTATUS 0x0014
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#define DISPC_IRQSTATUS 0x0018
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#define DISPC_IRQENABLE 0x001C
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#define DISPC_CONTROL 0x0040
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#define DISPC_CONFIG 0x0044
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#define DISPC_CAPABLE 0x0048
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#define DISPC_LINE_STATUS 0x005C
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#define DISPC_LINE_NUMBER 0x0060
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#define DISPC_GLOBAL_ALPHA 0x0074
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#define DISPC_CONTROL2 0x0238
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#define DISPC_CONFIG2 0x0620
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#define DISPC_DIVISOR 0x0804
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/* DISPC overlay registers */
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#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA0_OFFSET(n))
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#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA1_OFFSET(n))
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#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA0_UV_OFFSET(n))
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#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
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DISPC_BA1_UV_OFFSET(n))
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#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
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DISPC_POS_OFFSET(n))
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#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
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DISPC_SIZE_OFFSET(n))
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#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
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DISPC_ATTR_OFFSET(n))
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#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
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DISPC_ATTR2_OFFSET(n))
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#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIFO_THRESH_OFFSET(n))
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#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIFO_SIZE_STATUS_OFFSET(n))
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#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
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DISPC_ROW_INC_OFFSET(n))
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#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
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DISPC_PIX_INC_OFFSET(n))
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#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
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DISPC_WINDOW_SKIP_OFFSET(n))
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#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
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DISPC_TABLE_BA_OFFSET(n))
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#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_OFFSET(n))
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#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
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DISPC_FIR2_OFFSET(n))
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#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
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DISPC_PIC_SIZE_OFFSET(n))
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#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU0_OFFSET(n))
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#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU1_OFFSET(n))
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#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU2_0_OFFSET(n))
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#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
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DISPC_ACCU2_1_OFFSET(n))
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#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_H_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_HV_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_H2_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_HV2_OFFSET(n, i))
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#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_CONV_COEF_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_V_OFFSET(n, i))
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#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
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DISPC_FIR_COEF_V2_OFFSET(n, i))
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#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
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DISPC_PRELOAD_OFFSET(n))
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/* DISPC up/downsampling FIR filter coefficient structure */
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struct dispc_coef {
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s8 hc4_vc22;
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s8 hc3_vc2;
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u8 hc2_vc1;
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s8 hc1_vc0;
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s8 hc0_vc00;
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};
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const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
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/* DISPC manager/channel specific registers */
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static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x004C;
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case OMAP_DSS_CHANNEL_DIGIT:
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return 0x0050;
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03AC;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0054;
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case OMAP_DSS_CHANNEL_DIGIT:
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return 0x0058;
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03B0;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_TIMING_H(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0064;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x0400;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_TIMING_V(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0068;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x0404;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x006C;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x0408;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_DIVISORo(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0070;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x040C;
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default:
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BUG();
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}
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}
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/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
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static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x007C;
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case OMAP_DSS_CHANNEL_DIGIT:
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return 0x0078;
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03CC;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x01D4;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03C0;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x01D8;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03C4;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x01DC;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03C8;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0220;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03BC;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0224;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03B8;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
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{
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switch (channel) {
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case OMAP_DSS_CHANNEL_LCD:
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return 0x0228;
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case OMAP_DSS_CHANNEL_DIGIT:
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BUG();
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case OMAP_DSS_CHANNEL_LCD2:
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return 0x03B4;
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default:
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BUG();
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}
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}
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/* DISPC overlay register base addresses */
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static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0080;
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case OMAP_DSS_VIDEO1:
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return 0x00BC;
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case OMAP_DSS_VIDEO2:
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return 0x014C;
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case OMAP_DSS_VIDEO3:
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return 0x0300;
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default:
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BUG();
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}
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}
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/* DISPC overlay register offsets */
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static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0000;
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case OMAP_DSS_VIDEO3:
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return 0x0008;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0004;
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case OMAP_DSS_VIDEO3:
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return 0x000C;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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BUG();
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case OMAP_DSS_VIDEO1:
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return 0x0544;
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case OMAP_DSS_VIDEO2:
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return 0x04BC;
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case OMAP_DSS_VIDEO3:
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return 0x0310;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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BUG();
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case OMAP_DSS_VIDEO1:
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return 0x0548;
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case OMAP_DSS_VIDEO2:
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return 0x04C0;
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case OMAP_DSS_VIDEO3:
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return 0x0314;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0008;
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case OMAP_DSS_VIDEO3:
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return 0x009C;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x000C;
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case OMAP_DSS_VIDEO3:
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return 0x00A8;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0020;
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0010;
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case OMAP_DSS_VIDEO3:
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return 0x0070;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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BUG();
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case OMAP_DSS_VIDEO1:
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return 0x0568;
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case OMAP_DSS_VIDEO2:
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return 0x04DC;
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case OMAP_DSS_VIDEO3:
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return 0x032C;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0024;
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0014;
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case OMAP_DSS_VIDEO3:
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return 0x008C;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0028;
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0018;
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case OMAP_DSS_VIDEO3:
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return 0x0088;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x002C;
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x001C;
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case OMAP_DSS_VIDEO3:
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return 0x00A4;
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default:
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BUG();
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}
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}
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static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
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{
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switch (plane) {
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case OMAP_DSS_GFX:
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return 0x0030;
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case OMAP_DSS_VIDEO1:
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case OMAP_DSS_VIDEO2:
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return 0x0020;
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case OMAP_DSS_VIDEO3:
|
|
return 0x0098;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
return 0x0034;
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
case OMAP_DSS_VIDEO3:
|
|
BUG();
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
return 0x0038;
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
case OMAP_DSS_VIDEO3:
|
|
BUG();
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0024;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0090;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0580;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x055C;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0424;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0028;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0094;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
|
|
static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x002C;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0000;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0584;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0560;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0428;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0030;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0004;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0588;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0564;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x042C;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0034 + i * 0x8;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0010 + i * 0x8;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x058C + i * 0x8;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0568 + i * 0x8;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0430 + i * 0x8;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x0038 + i * 0x8;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0014 + i * 0x8;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0590 + i * 8;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x056C + i * 0x8;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0434 + i * 0x8;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4,} */
|
|
static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
case OMAP_DSS_VIDEO2:
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0074 + i * 0x4;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0124 + i * 0x4;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x00B4 + i * 0x4;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0050 + i * 0x4;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
|
|
static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
BUG();
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x05CC + i * 0x4;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x05A8 + i * 0x4;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x0470 + i * 0x4;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
|
|
static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
|
|
{
|
|
switch (plane) {
|
|
case OMAP_DSS_GFX:
|
|
return 0x01AC;
|
|
case OMAP_DSS_VIDEO1:
|
|
return 0x0174;
|
|
case OMAP_DSS_VIDEO2:
|
|
return 0x00E8;
|
|
case OMAP_DSS_VIDEO3:
|
|
return 0x00A0;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|
|
#endif
|