linux_dsm_epyc7002/drivers
Owen Chen 9d7e1a82b7 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
1. pcwibits: The integer bits of pcw for PLLs is extend to 8 bits,
   add a variable to indicate this change and
   backward-compatible.

2. fmin: The PLL frequency lower-bound is vary from 1GHz to
   1.5GHz, add a variable to indicate platform-dependent.

Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Reviewed-by: James Liao <jamesjj.liao@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 13:13:08 -07:00
..
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acpi device-dax for 5.1 2019-03-16 13:05:32 -07:00
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block for-5.1/block-post-20190315 2019-03-16 12:36:39 -07:00
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clk clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data 2019-04-11 13:13:08 -07:00
clocksource ARM: some cleanups, direct physical timer assignment, cache sanitization 2019-03-15 15:00:28 -07:00
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dax device-dax for 5.1 2019-03-16 13:05:32 -07:00
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hwtracing ARM updates for 5.1-rc1 2019-03-15 14:37:46 -07:00
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ntb Fixes for switchtec debugability and mapping table entries, NTB 2019-03-15 14:32:59 -07:00
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nvdimm device-dax for 5.1 2019-03-16 13:05:32 -07:00
nvme for-5.1/block-post-20190315 2019-03-16 12:36:39 -07:00
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s390 ARM: some cleanups, direct physical timer assignment, cache sanitization 2019-03-15 15:00:28 -07:00
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scsi SCSI misc on 20190315 2019-03-16 12:51:50 -07:00
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