mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 13:26:47 +07:00
4749c02b8d
On Marvell EBU platforms, when doing suspend/resume, the SDRAM window configuration must be saved on suspend, and restored on resume. However, it needs to be restored on resume *before* re-entering the kernel, because the SDRAM window configuration defines the layout of the memory. For this reason, it cannot simply be done in the ->suspend() and ->resume() hooks of the mvebu-mbus driver. Instead, it needs to be restored by the bootloader "boot info" mechanism used when resuming. This mechanism allows the kernel to define a list of (address, value) pairs when suspending, that the bootloader will restore on resume before jumping back into the kernel. This commit therefore adds a new function to the mvebu-mbus driver, called mvebu_mbus_save_cpu_target(), which will be called by the platform code to make the mvebu-mbus driver save the SDRAM window configuration in a way that can be understood by the bootloader "boot info" mechanism. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Link: https://lkml.kernel.org/r/1416585613-2113-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
80 lines
2.1 KiB
C
80 lines
2.1 KiB
C
/*
|
|
* Marvell MBUS common definitions.
|
|
*
|
|
* Copyright (C) 2008 Marvell Semiconductor
|
|
*
|
|
* This file is licensed under the terms of the GNU General Public
|
|
* License version 2. This program is licensed "as is" without any
|
|
* warranty of any kind, whether express or implied.
|
|
*/
|
|
|
|
#ifndef __LINUX_MBUS_H
|
|
#define __LINUX_MBUS_H
|
|
|
|
struct resource;
|
|
|
|
struct mbus_dram_target_info
|
|
{
|
|
/*
|
|
* The 4-bit MBUS target ID of the DRAM controller.
|
|
*/
|
|
u8 mbus_dram_target_id;
|
|
|
|
/*
|
|
* The base address, size, and MBUS attribute ID for each
|
|
* of the possible DRAM chip selects. Peripherals are
|
|
* required to support at least 4 decode windows.
|
|
*/
|
|
int num_cs;
|
|
struct mbus_dram_window {
|
|
u8 cs_index;
|
|
u8 mbus_attr;
|
|
u32 base;
|
|
u32 size;
|
|
} cs[4];
|
|
};
|
|
|
|
/* Flags for PCI/PCIe address decoding regions */
|
|
#define MVEBU_MBUS_PCI_IO 0x1
|
|
#define MVEBU_MBUS_PCI_MEM 0x2
|
|
#define MVEBU_MBUS_PCI_WA 0x3
|
|
|
|
/*
|
|
* Magic value that explicits that we don't need a remapping-capable
|
|
* address decoding window.
|
|
*/
|
|
#define MVEBU_MBUS_NO_REMAP (0xffffffff)
|
|
|
|
/* Maximum size of a mbus window name */
|
|
#define MVEBU_MBUS_MAX_WINNAME_SZ 32
|
|
|
|
/*
|
|
* The Marvell mbus is to be found only on SOCs from the Orion family
|
|
* at the moment. Provide a dummy stub for other architectures.
|
|
*/
|
|
#ifdef CONFIG_PLAT_ORION
|
|
extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
|
|
#else
|
|
static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
|
|
{
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
int mvebu_mbus_save_cpu_target(u32 *store_addr);
|
|
void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
|
|
void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
|
|
int mvebu_mbus_add_window_remap_by_id(unsigned int target,
|
|
unsigned int attribute,
|
|
phys_addr_t base, size_t size,
|
|
phys_addr_t remap);
|
|
int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
|
|
phys_addr_t base, size_t size);
|
|
int mvebu_mbus_del_window(phys_addr_t base, size_t size);
|
|
int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
|
|
size_t mbus_size, phys_addr_t sdram_phys_base,
|
|
size_t sdram_size);
|
|
int mvebu_mbus_dt_init(bool is_coherent);
|
|
|
|
#endif /* __LINUX_MBUS_H */
|