mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-06 19:16:39 +07:00
e89f5b3701
Revert the clearing of __GFP_ZERO in dma_alloc_attrs and move it to
dma_direct_alloc for now. While most common architectures always zero dma
cohereny allocations (and x86 did so since day one) this is not documented
and at least arc and s390 do not zero without the explicit __GFP_ZERO
argument.
Fixes: 57bf5a8963
("dma-mapping: clear harmful GFP_* flags in common code")
Reported-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
Reported-by: Sebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Evgeniy Didin <Evgeniy.Didin@synopsys.com>
Cc: iommu@lists.linux-foundation.org
Link: https://lkml.kernel.org/r/20180328133535.17302-2-hch@lst.de
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* DMA operations that map physical memory directly without using an IOMMU or
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* flushing caches.
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/dma-direct.h>
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#include <linux/scatterlist.h>
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#include <linux/dma-contiguous.h>
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#include <linux/pfn.h>
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#include <linux/set_memory.h>
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#define DIRECT_MAPPING_ERROR 0
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/*
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* Most architectures use ZONE_DMA for the first 16 Megabytes, but
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* some use it for entirely different regions:
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*/
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#ifndef ARCH_ZONE_DMA_BITS
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#define ARCH_ZONE_DMA_BITS 24
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#endif
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/*
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* For AMD SEV all DMA must be to unencrypted addresses.
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*/
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static inline bool force_dma_unencrypted(void)
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{
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return sev_active();
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}
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static bool
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check_addr(struct device *dev, dma_addr_t dma_addr, size_t size,
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const char *caller)
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{
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if (unlikely(dev && !dma_capable(dev, dma_addr, size))) {
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if (*dev->dma_mask >= DMA_BIT_MASK(32)) {
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dev_err(dev,
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"%s: overflow %pad+%zu of device mask %llx\n",
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caller, &dma_addr, size, *dev->dma_mask);
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}
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return false;
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}
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return true;
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}
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static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
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{
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dma_addr_t addr = force_dma_unencrypted() ?
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__phys_to_dma(dev, phys) : phys_to_dma(dev, phys);
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return addr + size - 1 <= dev->coherent_dma_mask;
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}
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void *dma_direct_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
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gfp_t gfp, unsigned long attrs)
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{
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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int page_order = get_order(size);
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struct page *page = NULL;
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void *ret;
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/* we always manually zero the memory once we are done: */
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gfp &= ~__GFP_ZERO;
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/* GFP_DMA32 and GFP_DMA are no ops without the corresponding zones: */
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if (dev->coherent_dma_mask <= DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
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gfp |= GFP_DMA;
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if (dev->coherent_dma_mask <= DMA_BIT_MASK(32) && !(gfp & GFP_DMA))
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gfp |= GFP_DMA32;
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again:
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/* CMA can be used only in the context which permits sleeping */
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if (gfpflags_allow_blocking(gfp)) {
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page = dma_alloc_from_contiguous(dev, count, page_order, gfp);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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dma_release_from_contiguous(dev, page, count);
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page = NULL;
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}
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}
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if (!page)
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page = alloc_pages_node(dev_to_node(dev), gfp, page_order);
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if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
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__free_pages(page, page_order);
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page = NULL;
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if (dev->coherent_dma_mask < DMA_BIT_MASK(32) &&
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!(gfp & GFP_DMA)) {
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gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
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goto again;
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}
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}
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if (!page)
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return NULL;
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ret = page_address(page);
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if (force_dma_unencrypted()) {
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set_memory_decrypted((unsigned long)ret, 1 << page_order);
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*dma_handle = __phys_to_dma(dev, page_to_phys(page));
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} else {
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*dma_handle = phys_to_dma(dev, page_to_phys(page));
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}
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memset(ret, 0, size);
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return ret;
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}
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/*
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* NOTE: this function must never look at the dma_addr argument, because we want
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* to be able to use it as a helper for iommu implementations as well.
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*/
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void dma_direct_free(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_addr, unsigned long attrs)
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{
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unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
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unsigned int page_order = get_order(size);
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if (force_dma_unencrypted())
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set_memory_encrypted((unsigned long)cpu_addr, 1 << page_order);
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if (!dma_release_from_contiguous(dev, virt_to_page(cpu_addr), count))
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free_pages((unsigned long)cpu_addr, page_order);
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}
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static dma_addr_t dma_direct_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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dma_addr_t dma_addr = phys_to_dma(dev, page_to_phys(page)) + offset;
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if (!check_addr(dev, dma_addr, size, __func__))
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return DIRECT_MAPPING_ERROR;
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return dma_addr;
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}
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static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
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int nents, enum dma_data_direction dir, unsigned long attrs)
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{
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int i;
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struct scatterlist *sg;
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for_each_sg(sgl, sg, nents, i) {
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BUG_ON(!sg_page(sg));
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sg_dma_address(sg) = phys_to_dma(dev, sg_phys(sg));
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if (!check_addr(dev, sg_dma_address(sg), sg->length, __func__))
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return 0;
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sg_dma_len(sg) = sg->length;
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}
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return nents;
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}
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int dma_direct_supported(struct device *dev, u64 mask)
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{
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#ifdef CONFIG_ZONE_DMA
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if (mask < DMA_BIT_MASK(ARCH_ZONE_DMA_BITS))
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return 0;
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#else
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/*
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* Because 32-bit DMA masks are so common we expect every architecture
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* to be able to satisfy them - either by not supporting more physical
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* memory, or by providing a ZONE_DMA32. If neither is the case, the
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* architecture needs to use an IOMMU instead of the direct mapping.
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*/
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if (mask < DMA_BIT_MASK(32))
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return 0;
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#endif
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return 1;
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}
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static int dma_direct_mapping_error(struct device *dev, dma_addr_t dma_addr)
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{
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return dma_addr == DIRECT_MAPPING_ERROR;
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}
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const struct dma_map_ops dma_direct_ops = {
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.alloc = dma_direct_alloc,
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.free = dma_direct_free,
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.map_page = dma_direct_map_page,
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.map_sg = dma_direct_map_sg,
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.dma_supported = dma_direct_supported,
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.mapping_error = dma_direct_mapping_error,
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.is_phys = 1,
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};
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EXPORT_SYMBOL(dma_direct_ops);
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