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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9d35dc3006
Current C-SKY ASID mechanism is from mips and it doesn't work well with multi-cores. ASID per core mechanism is not suitable for C-SKY SMP tlb maintain operations, eg: tlbi.vas need share the same asid in all processors and it'll invalid the tlb entry in all cores with the same asid. This patch is prepare for new ASID mechanism. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Cc: Arnd Bergmann <arnd@arndb.de>
40 lines
991 B
C
40 lines
991 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
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#ifndef __ASM_CSKY_MMU_CONTEXT_H
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#define __ASM_CSKY_MMU_CONTEXT_H
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#include <asm-generic/mm_hooks.h>
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#include <asm/setup.h>
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#include <asm/page.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <abi/ckmmu.h>
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#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
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setup_pgd(__pa(pgd), false)
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#define TLBMISS_HANDLER_SETUP_PGD_KERNEL(pgd) \
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setup_pgd(__pa(pgd), true)
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#define init_new_context(tsk,mm) 0
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#define activate_mm(prev,next) switch_mm(prev, next, current)
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#define destroy_context(mm) do {} while (0)
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#define enter_lazy_tlb(mm, tsk) do {} while (0)
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#define deactivate_mm(tsk, mm) do {} while (0)
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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if (prev != next)
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tlb_invalid_all();
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TLBMISS_HANDLER_SETUP_PGD(next->pgd);
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}
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#endif /* __ASM_CSKY_MMU_CONTEXT_H */
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