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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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03db0729b7
The two GPIO controllers are always mapped to the same virtual address across all MSM devices. Instead of selecting this at compile time, determine the physical address at runtime, eliminating yet something else preventing multiple MSM targets from being compiled into the same kernel. Change-Id: I1672219d978ab6243526adeda6badf49472baa27 Signed-off-by: David Brown <davidb@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
138 lines
4.0 KiB
C
138 lines
4.0 KiB
C
/*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2008-2011 Code Aurora Forum. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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* The MSM peripherals are spread all over across 768MB of physical
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* space, which makes just having a simple IO_ADDRESS macro to slide
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* them into the right virtual location rough. Instead, we will
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* provide a master phys->virt mapping for peripherals here.
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*
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*/
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#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H
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#define __ASM_ARCH_MSM_IOMAP_8X50_H
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/* Physical base address and size of peripherals.
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* Ordered by the virtual base addresses they will be mapped at.
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*
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* MSM_VIC_BASE must be an value that can be loaded via a "mov"
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* instruction, otherwise entry-macro.S will not compile.
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*
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* If you add or remove entries here, you'll want to edit the
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* msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
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* changes.
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*
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*/
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#define MSM_VIC_BASE IOMEM(0xE0000000)
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#define MSM_VIC_PHYS 0xAC000000
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#define MSM_VIC_SIZE SZ_4K
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#define QSD8X50_CSR_PHYS 0xAC100000
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#define QSD8X50_CSR_SIZE SZ_4K
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#define MSM_DMOV_BASE IOMEM(0xE0002000)
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#define MSM_DMOV_PHYS 0xA9700000
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#define MSM_DMOV_SIZE SZ_4K
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#define QSD8X50_GPIO1_PHYS 0xA9000000
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#define QSD8X50_GPIO1_SIZE SZ_4K
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#define QSD8X50_GPIO2_PHYS 0xA9100000
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#define QSD8X50_GPIO2_SIZE SZ_4K
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#define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
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#define MSM_CLK_CTL_PHYS 0xA8600000
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#define MSM_CLK_CTL_SIZE SZ_4K
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#define MSM_SIRC_BASE IOMEM(0xE1006000)
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#define MSM_SIRC_PHYS 0xAC200000
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#define MSM_SIRC_SIZE SZ_4K
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#define MSM_SCPLL_BASE IOMEM(0xE1007000)
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#define MSM_SCPLL_PHYS 0xA8800000
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#define MSM_SCPLL_SIZE SZ_4K
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#ifdef CONFIG_MSM_SOC_REV_A
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#define MSM_SMI_BASE 0xE0000000
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#else
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#define MSM_SMI_BASE 0x00000000
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#endif
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#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
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#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000)
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#define MSM_SHARED_RAM_SIZE SZ_1M
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#define MSM_UART1_PHYS 0xA9A00000
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#define MSM_UART1_SIZE SZ_4K
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#define MSM_UART2_PHYS 0xA9B00000
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#define MSM_UART2_SIZE SZ_4K
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#define MSM_UART3_PHYS 0xA9C00000
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#define MSM_UART3_SIZE SZ_4K
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#ifdef CONFIG_MSM_DEBUG_UART
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#define MSM_DEBUG_UART_BASE 0xE1000000
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#if CONFIG_MSM_DEBUG_UART == 1
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#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
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#elif CONFIG_MSM_DEBUG_UART == 2
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#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
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#elif CONFIG_MSM_DEBUG_UART == 3
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#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
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#endif
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#define MSM_DEBUG_UART_SIZE SZ_4K
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#endif
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#define MSM_MDC_BASE IOMEM(0xE0200000)
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#define MSM_MDC_PHYS 0xAA500000
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#define MSM_MDC_SIZE SZ_1M
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#define MSM_AD5_BASE IOMEM(0xE0300000)
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#define MSM_AD5_PHYS 0xAC000000
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#define MSM_AD5_SIZE (SZ_1M*13)
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#define MSM_I2C_SIZE SZ_4K
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#define MSM_I2C_PHYS 0xA9900000
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#define MSM_HSUSB_PHYS 0xA0800000
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#define MSM_HSUSB_SIZE SZ_1K
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#define MSM_NAND_PHYS 0xA0A00000
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#define MSM_TSIF_PHYS (0xa0100000)
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#define MSM_TSIF_SIZE (0x200)
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#define MSM_TSSC_PHYS 0xAA300000
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#define MSM_UART1DM_PHYS 0xA0200000
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#define MSM_UART2DM_PHYS 0xA0900000
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#define MSM_SDC1_PHYS 0xA0300000
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#define MSM_SDC1_SIZE SZ_4K
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#define MSM_SDC2_PHYS 0xA0400000
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#define MSM_SDC2_SIZE SZ_4K
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#define MSM_SDC3_PHYS 0xA0500000
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#define MSM_SDC3_SIZE SZ_4K
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#define MSM_SDC4_PHYS 0xA0600000
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#define MSM_SDC4_SIZE SZ_4K
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#endif
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