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9d2027830c
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
76 lines
1.8 KiB
Plaintext
76 lines
1.8 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP SoC that are not
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* common to all Armada SoCs.
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*/
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/include/ "armada-370-xp.dtsi"
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/ {
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model = "Marvell Armada XP family SoC";
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compatible = "marvell,armadaxp", "marvell,armada-370-xp";
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mpic: interrupt-controller@d0020000 {
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reg = <0xd0020a00 0x1d0>,
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<0xd0021870 0x58>;
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};
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soc {
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serial@d0012200 {
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compatible = "ns16550";
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reg = <0xd0012200 0x100>;
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reg-shift = <2>;
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interrupts = <43>;
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status = "disabled";
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};
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serial@d0012300 {
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compatible = "ns16550";
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reg = <0xd0012300 0x100>;
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reg-shift = <2>;
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interrupts = <44>;
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status = "disabled";
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};
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timer@d0020300 {
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marvell,timer-25Mhz;
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};
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coreclk: mvebu-sar@d0018230 {
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compatible = "marvell,armada-xp-core-clock";
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reg = <0xd0018230 0x08>;
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#clock-cells = <1>;
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};
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>;
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clocks = <&coreclk 1>;
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};
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gateclk: clock-gating-control@d0018220 {
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compatible = "marvell,armada-xp-gating-clock";
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reg = <0xd0018220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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system-controller@d0018200 {
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compatible = "marvell,armada-370-xp-system-controller";
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reg = <0xd0018200 0x500>;
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};
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};
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};
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