mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 15:26:54 +07:00
1bb5fcb1e2
Upcoming change to DT compiler is going to complain about nodes which have a reg property, but have not defined the address in their name. This patch fixes following type of warnings for OMAP2 clock nodes: Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck has a reg or ranges property, but no unit name Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
345 lines
7.6 KiB
Plaintext
345 lines
7.6 KiB
Plaintext
/*
|
|
* Device Tree Source for OMAP2430 clock data
|
|
*
|
|
* Copyright (C) 2014 Texas Instruments, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
&scm_clocks {
|
|
mcbsp3_mux_fck: mcbsp3_mux_fck@78 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_96m_ck>, <&mcbsp_clks>;
|
|
reg = <0x78>;
|
|
};
|
|
|
|
mcbsp3_fck: mcbsp3_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
|
|
};
|
|
|
|
mcbsp4_mux_fck: mcbsp4_mux_fck@78 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_96m_ck>, <&mcbsp_clks>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x78>;
|
|
};
|
|
|
|
mcbsp4_fck: mcbsp4_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
|
|
};
|
|
|
|
mcbsp5_mux_fck: mcbsp5_mux_fck@78 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&func_96m_ck>, <&mcbsp_clks>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x78>;
|
|
};
|
|
|
|
mcbsp5_fck: mcbsp5_fck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
|
|
};
|
|
};
|
|
|
|
&prcm_clocks {
|
|
iva2_1_gate_ick: iva2_1_gate_ick@800 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&dsp_fck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0800>;
|
|
};
|
|
|
|
iva2_1_div_ick: iva2_1_div_ick@840 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-divider-clock";
|
|
clocks = <&dsp_fck>;
|
|
ti,bit-shift = <5>;
|
|
ti,max-div = <3>;
|
|
reg = <0x0840>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
iva2_1_ick: iva2_1_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
|
|
};
|
|
|
|
mdm_gate_ick: mdm_gate_ick@c10 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-interface-clock";
|
|
clocks = <&core_ck>;
|
|
ti,bit-shift = <0>;
|
|
reg = <0x0c10>;
|
|
};
|
|
|
|
mdm_div_ick: mdm_div_ick@c40 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-divider-clock";
|
|
clocks = <&core_ck>;
|
|
reg = <0x0c40>;
|
|
ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
|
|
};
|
|
|
|
mdm_ick: mdm_ick {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
|
|
};
|
|
|
|
mdm_osc_ck: mdm_osc_ck@c00 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&osc_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0c00>;
|
|
};
|
|
|
|
mcbsp3_ick: mcbsp3_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mcbsp3_gate_fck: mcbsp3_gate_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&mcbsp_clks>;
|
|
ti,bit-shift = <3>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mcbsp4_ick: mcbsp4_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mcbsp4_gate_fck: mcbsp4_gate_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&mcbsp_clks>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mcbsp5_ick: mcbsp5_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <5>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mcbsp5_gate_fck: mcbsp5_gate_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-gate-clock";
|
|
clocks = <&mcbsp_clks>;
|
|
ti,bit-shift = <5>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mcspi3_ick: mcspi3_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mcspi3_fck: mcspi3_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_48m_ck>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
icr_ick: icr_ick@410 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&sys_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x0410>;
|
|
};
|
|
|
|
i2chs1_fck: i2chs1_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap2430-interface-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <19>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
i2chs2_fck: i2chs2_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap2430-interface-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <20>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
usbhs_ick: usbhs_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&core_l3_ck>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mmchs1_ick: mmchs1_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mmchs1_fck: mmchs1_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mmchs2_ick: mmchs2_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mmchs2_fck: mmchs2_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_96m_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
gpio5_ick: gpio5_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
gpio5_fck: gpio5_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mdm_intc_ick: mdm_intc_ick@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap3-interface-clock";
|
|
clocks = <&l4_ck>;
|
|
ti,bit-shift = <11>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
mmchsdb1_fck: mmchsdb1_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <16>;
|
|
reg = <0x0204>;
|
|
};
|
|
|
|
mmchsdb2_fck: mmchsdb2_fck@204 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,wait-gate-clock";
|
|
clocks = <&func_32k_ck>;
|
|
ti,bit-shift = <17>;
|
|
reg = <0x0204>;
|
|
};
|
|
};
|
|
|
|
&prcm_clockdomains {
|
|
gfx_clkdm: gfx_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&gfx_ick>;
|
|
};
|
|
|
|
core_l3_clkdm: core_l3_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
|
|
};
|
|
|
|
wkup_clkdm: wkup_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
|
|
<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
|
|
<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
|
|
<&icr_ick>;
|
|
};
|
|
|
|
dss_clkdm: dss_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&dss_ick>, <&dss_54m_fck>;
|
|
};
|
|
|
|
core_l4_clkdm: core_l4_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
|
|
<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
|
|
<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
|
|
<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
|
|
<&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
|
|
<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
|
|
<&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
|
|
<&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
|
|
<&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
|
|
<&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
|
|
<&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
|
|
<&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
|
|
<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
|
|
<&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
|
|
<&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
|
|
<&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
|
|
<&mmchsdb2_fck>;
|
|
};
|
|
|
|
mdm_clkdm: mdm_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&mdm_osc_ck>;
|
|
};
|
|
};
|
|
|
|
&func_96m_ck {
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&apll96_ck>, <&alt_ck>;
|
|
ti,bit-shift = <4>;
|
|
reg = <0x0540>;
|
|
};
|
|
|
|
&dsp_div_fck {
|
|
ti,max-div = <4>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
&ssi_ssr_sst_div_fck {
|
|
ti,max-div = <5>;
|
|
ti,index-starts-at-one;
|
|
};
|