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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9d0fa6c5f4
In the case of x2apic cluster mode we can group IPI register writes based on the cluster group instead of individual per-cpu destination messages. This reduces the apic register writes and reduces the amount of IPI messages (in the best case we can reduce it by a factor of 16). With this change, the cost of flush_tlb_others(), with the flush tlb IPI being sent from a cpu in the socket-1 to all the logical cpus in socket-2 (on a Westmere-EX system that has 20 logical cpus in a socket) is 3x times better now (compared to the former 'send one-by-one' algorithm). Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: steiner@sgi.com Cc: yinghai@kernel.org Link: http://lkml.kernel.org/r/20110519234637.512271057@sbsiddha-MOBL3.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
330 lines
7.9 KiB
C
330 lines
7.9 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/dmar.h>
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#include <linux/cpu.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
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static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
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static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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return x2apic_enabled();
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}
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/*
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* need to use more than cpu 0, because we need more vectors when
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* MSI-X are used.
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*/
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpu_online_mask;
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}
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/*
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* for now each logical cpu is in its own vector allocation domain.
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*/
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void
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__x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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native_x2apic_icr_write(cfg, apicid);
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}
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static inline u32 x2apic_cluster(int cpu)
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{
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return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
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}
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static void
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__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
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{
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struct cpumask *cpus_in_cluster_ptr;
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struct cpumask *ipi_mask_ptr;
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unsigned int cpu, this_cpu;
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unsigned long flags;
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u32 dest;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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this_cpu = smp_processor_id();
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/*
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* We are to modify mask, so we need an own copy
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* and be sure it's manipulated with irq off.
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*/
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ipi_mask_ptr = __raw_get_cpu_var(ipi_mask);
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cpumask_copy(ipi_mask_ptr, mask);
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/*
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* The idea is to send one IPI per cluster.
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*/
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for_each_cpu(cpu, ipi_mask_ptr) {
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unsigned long i;
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cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
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dest = 0;
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/* Collect cpus in cluster. */
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for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
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if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
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dest |= per_cpu(x86_cpu_to_logical_apicid, i);
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}
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if (!dest)
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continue;
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__x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
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/*
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* Cluster sibling cpus should be discared now so
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* we would not send IPI them second time.
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*/
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cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
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}
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static void
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x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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__x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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* We're using fixed IRQ delivery, can only return one logical APIC ID.
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* May as well be the first.
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*/
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int cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int
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x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one logical APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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}
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static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x)
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{
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unsigned int id;
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id = x;
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = id;
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return x;
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}
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static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
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__cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
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for_each_online_cpu(cpu) {
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if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
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continue;
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__cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu));
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__cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu));
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}
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}
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/*
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* At CPU state changes, update the x2apic cluster sibling info.
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*/
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static int __cpuinit
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update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu)
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{
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unsigned int this_cpu = (unsigned long)hcpu;
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unsigned int cpu;
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int err = 0;
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switch (action) {
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case CPU_UP_PREPARE:
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if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu),
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GFP_KERNEL)) {
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err = -ENOMEM;
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} else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu),
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GFP_KERNEL)) {
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free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
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err = -ENOMEM;
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}
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break;
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case CPU_UP_CANCELED:
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case CPU_UP_CANCELED_FROZEN:
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case CPU_DEAD:
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for_each_online_cpu(cpu) {
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if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
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continue;
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__cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu));
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__cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu));
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}
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free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
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free_cpumask_var(per_cpu(ipi_mask, this_cpu));
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break;
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}
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return notifier_from_errno(err);
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}
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static struct notifier_block __refdata x2apic_cpu_notifier = {
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.notifier_call = update_clusterinfo,
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};
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static int x2apic_init_cpu_notifier(void)
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{
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int cpu = smp_processor_id();
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zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL);
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zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL);
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BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu));
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__cpu_set(cpu, per_cpu(cpus_in_cluster, cpu));
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register_hotcpu_notifier(&x2apic_cpu_notifier);
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return 1;
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}
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static int x2apic_cluster_probe(void)
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{
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if (x2apic_mode)
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return x2apic_init_cpu_notifier();
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else
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return 0;
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}
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struct apic apic_x2apic_cluster = {
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.name = "cluster x2apic",
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.probe = x2apic_cluster_probe,
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.apic_id_registered = x2apic_apic_id_registered,
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.irq_delivery_mode = dest_LowestPrio,
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.irq_dest_mode = 1, /* logical */
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.target_cpus = x2apic_target_cpus,
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.disable_esr = 0,
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.dest_logical = APIC_DEST_LOGICAL,
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.check_apicid_used = NULL,
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.check_apicid_present = NULL,
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.vector_allocation_domain = x2apic_vector_allocation_domain,
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.init_apic_ldr = init_x2apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.multi_timer_check = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = x2apic_cluster_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_cluster_phys_get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_self = x2apic_send_IPI_self,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = NULL,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = NULL,
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.read = native_apic_msr_read,
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.write = native_apic_msr_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.wait_icr_idle = native_x2apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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