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9d0ef5ea04
This provides for the case where userspace maps an I/O device into the address range of a memory slot using a VM_PFNMAP mapping. In that case, we work out the pfn from vma->vm_pgoff, and record the cache enable bits from vma->vm_page_prot in two low-order bits in the slot_phys array entries. Then, in kvmppc_h_enter() we check that the cache bits in the HPTE that the guest wants to insert match the cache bits in the slot_phys array entry. However, we do allow the guest to create what it thinks is a non-cacheable or write-through mapping to memory that is actually cacheable, so that we can use normal system memory as part of an emulated device later on. In that case the actual HPTE we insert is a cacheable HPTE. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Avi Kivity <avi@redhat.com>
153 lines
4.2 KiB
C
153 lines
4.2 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* Copyright SUSE Linux Products GmbH 2010
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*
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* Authors: Alexander Graf <agraf@suse.de>
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*/
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#ifndef __ASM_KVM_BOOK3S_64_H__
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#define __ASM_KVM_BOOK3S_64_H__
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#ifdef CONFIG_KVM_BOOK3S_PR
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static inline struct kvmppc_book3s_shadow_vcpu *svcpu_get(struct kvm_vcpu *vcpu)
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{
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preempt_disable();
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return &get_paca()->shadow_vcpu;
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}
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static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
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{
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preempt_enable();
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}
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#endif
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#define SPAPR_TCE_SHIFT 12
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#ifdef CONFIG_KVM_BOOK3S_64_HV
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/* For now use fixed-size 16MB page table */
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#define HPT_ORDER 24
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#define HPT_NPTEG (1ul << (HPT_ORDER - 7)) /* 128B per pteg */
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#define HPT_NPTE (HPT_NPTEG << 3) /* 8 PTEs per PTEG */
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#define HPT_HASH_MASK (HPT_NPTEG - 1)
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#endif
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/*
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* We use a lock bit in HPTE dword 0 to synchronize updates and
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* accesses to each HPTE, and another bit to indicate non-present
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* HPTEs.
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*/
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#define HPTE_V_HVLOCK 0x40UL
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static inline long try_lock_hpte(unsigned long *hpte, unsigned long bits)
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{
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unsigned long tmp, old;
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asm volatile(" ldarx %0,0,%2\n"
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" and. %1,%0,%3\n"
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" bne 2f\n"
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" ori %0,%0,%4\n"
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" stdcx. %0,0,%2\n"
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" beq+ 2f\n"
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" li %1,%3\n"
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"2: isync"
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: "=&r" (tmp), "=&r" (old)
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: "r" (hpte), "r" (bits), "i" (HPTE_V_HVLOCK)
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: "cc", "memory");
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return old == 0;
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}
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static inline unsigned long compute_tlbie_rb(unsigned long v, unsigned long r,
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unsigned long pte_index)
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{
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unsigned long rb, va_low;
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rb = (v & ~0x7fUL) << 16; /* AVA field */
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va_low = pte_index >> 3;
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if (v & HPTE_V_SECONDARY)
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va_low = ~va_low;
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/* xor vsid from AVA */
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if (!(v & HPTE_V_1TB_SEG))
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va_low ^= v >> 12;
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else
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va_low ^= v >> 24;
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va_low &= 0x7ff;
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if (v & HPTE_V_LARGE) {
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rb |= 1; /* L field */
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if (cpu_has_feature(CPU_FTR_ARCH_206) &&
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(r & 0xff000)) {
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/* non-16MB large page, must be 64k */
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/* (masks depend on page size) */
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rb |= 0x1000; /* page encoding in LP field */
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
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rb |= (va_low & 0xfe); /* AVAL field (P7 doesn't seem to care) */
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}
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} else {
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/* 4kB page */
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of VA */
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}
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rb |= (v >> 54) & 0x300; /* B field */
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return rb;
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}
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static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
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{
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/* only handle 4k, 64k and 16M pages for now */
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if (!(h & HPTE_V_LARGE))
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return 1ul << 12; /* 4k page */
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if ((l & 0xf000) == 0x1000 && cpu_has_feature(CPU_FTR_ARCH_206))
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return 1ul << 16; /* 64k page */
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if ((l & 0xff000) == 0)
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return 1ul << 24; /* 16M page */
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return 0; /* error */
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}
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static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
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{
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unsigned int wimg = ptel & HPTE_R_WIMG;
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/* Handle SAO */
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if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&
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cpu_has_feature(CPU_FTR_ARCH_206))
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wimg = HPTE_R_M;
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if (!io_type)
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return wimg == HPTE_R_M;
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return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;
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}
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/* Return HPTE cache control bits corresponding to Linux pte bits */
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static inline unsigned long hpte_cache_bits(unsigned long pte_val)
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{
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#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W
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return pte_val & (HPTE_R_W | HPTE_R_I);
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#else
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return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +
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((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);
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#endif
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}
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static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
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unsigned long pagesize)
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{
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unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
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if (pagesize <= PAGE_SIZE)
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return 1;
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return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
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}
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#endif /* __ASM_KVM_BOOK3S_64_H__ */
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