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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dea978632e
The 64bit implementations need the same wrappers around __default_send_IPI_shortcut() as 32bit. Move them out of the 32bit section. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20190722105220.951534451@linutronix.de
331 lines
7.5 KiB
C
331 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/cpumask.h>
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#include <linux/smp.h>
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#include "local.h"
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DEFINE_STATIC_KEY_FALSE(apic_use_ipi_shorthand);
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#ifdef CONFIG_SMP
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static int apic_ipi_shorthand_off __ro_after_init;
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static __init int apic_ipi_shorthand(char *str)
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{
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get_option(&str, &apic_ipi_shorthand_off);
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return 1;
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}
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__setup("no_ipi_broadcast=", apic_ipi_shorthand);
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static int __init print_ipi_mode(void)
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{
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pr_info("IPI shorthand broadcast: %s\n",
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apic_ipi_shorthand_off ? "disabled" : "enabled");
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return 0;
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}
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late_initcall(print_ipi_mode);
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void apic_smt_update(void)
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{
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/*
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* Do not switch to broadcast mode if:
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* - Disabled on the command line
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* - Only a single CPU is online
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* - Not all present CPUs have been at least booted once
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*
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* The latter is important as the local APIC might be in some
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* random state and a broadcast might cause havoc. That's
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* especially true for NMI broadcasting.
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*/
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if (apic_ipi_shorthand_off || num_online_cpus() == 1 ||
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!cpumask_equal(cpu_present_mask, &cpus_booted_once_mask)) {
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static_branch_disable(&apic_use_ipi_shorthand);
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} else {
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static_branch_enable(&apic_use_ipi_shorthand);
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}
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}
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void apic_send_IPI_allbutself(unsigned int vector)
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{
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if (num_online_cpus() < 2)
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return;
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if (static_branch_likely(&apic_use_ipi_shorthand))
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apic->send_IPI_allbutself(vector);
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else
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apic->send_IPI_mask_allbutself(cpu_online_mask, vector);
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}
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/*
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* Send a 'reschedule' IPI to another CPU. It goes straight through and
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* wastes no time serializing anything. Worst case is that we lose a
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* reschedule ...
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*/
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void native_smp_send_reschedule(int cpu)
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{
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if (unlikely(cpu_is_offline(cpu))) {
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WARN(1, "sched: Unexpected reschedule of offline CPU#%d!\n", cpu);
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return;
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}
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apic->send_IPI(cpu, RESCHEDULE_VECTOR);
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}
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void native_send_call_func_single_ipi(int cpu)
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{
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apic->send_IPI(cpu, CALL_FUNCTION_SINGLE_VECTOR);
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}
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void native_send_call_func_ipi(const struct cpumask *mask)
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{
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if (static_branch_likely(&apic_use_ipi_shorthand)) {
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unsigned int cpu = smp_processor_id();
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if (!cpumask_or_equal(mask, cpumask_of(cpu), cpu_online_mask))
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goto sendmask;
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if (cpumask_test_cpu(cpu, mask))
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apic->send_IPI_all(CALL_FUNCTION_VECTOR);
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else if (num_online_cpus() > 1)
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apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR);
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return;
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}
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sendmask:
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apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR);
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}
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#endif /* CONFIG_SMP */
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static inline int __prepare_ICR2(unsigned int mask)
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{
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return SET_APIC_DEST_FIELD(mask);
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}
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static inline void __xapic_wait_icr_idle(void)
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{
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while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
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cpu_relax();
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}
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void __default_send_IPI_shortcut(unsigned int shortcut, int vector)
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{
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/*
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* Subtle. In the case of the 'never do double writes' workaround
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* we have to lock out interrupts to be safe. As we don't care
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* of the value read we use an atomic rmw access to avoid costly
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* cli/sti. Otherwise we use an even cheaper single atomic write
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* to the APIC.
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*/
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unsigned int cfg;
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/*
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* Wait for idle.
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*/
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if (unlikely(vector == NMI_VECTOR))
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safe_apic_wait_icr_idle();
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else
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__xapic_wait_icr_idle();
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/*
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* No need to touch the target chip field. Also the destination
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* mode is ignored when a shorthand is used.
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*/
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cfg = __prepare_ICR(shortcut, vector, 0);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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native_apic_mem_write(APIC_ICR, cfg);
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}
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/*
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* This is used to send an IPI with no shorthand notation (the destination is
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* specified in bits 56 to 63 of the ICR).
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*/
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void __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest)
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{
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unsigned long cfg;
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/*
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* Wait for idle.
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*/
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if (unlikely(vector == NMI_VECTOR))
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safe_apic_wait_icr_idle();
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else
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__xapic_wait_icr_idle();
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/*
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* prepare target chip field
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*/
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cfg = __prepare_ICR2(mask);
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native_apic_mem_write(APIC_ICR2, cfg);
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/*
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* program the ICR
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*/
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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native_apic_mem_write(APIC_ICR, cfg);
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}
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void default_send_IPI_single_phys(int cpu, int vector)
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{
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unsigned long flags;
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local_irq_save(flags);
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__default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, cpu),
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vector, APIC_DEST_PHYSICAL);
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local_irq_restore(flags);
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}
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void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector)
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{
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unsigned long query_cpu;
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unsigned long flags;
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/*
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* Hack. The clustered APIC addressing mode doesn't allow us to send
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* to an arbitrary mask, so I do a unicast to each CPU instead.
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* - mbligh
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*/
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask) {
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__default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
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query_cpu), vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask,
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int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int query_cpu;
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unsigned long flags;
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/* See Hack comment above */
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask) {
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if (query_cpu == this_cpu)
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continue;
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__default_send_IPI_dest_field(per_cpu(x86_cpu_to_apicid,
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query_cpu), vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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/*
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* Helper function for APICs which insist on cpumasks
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*/
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void default_send_IPI_single(int cpu, int vector)
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{
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apic->send_IPI_mask(cpumask_of(cpu), vector);
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}
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void default_send_IPI_allbutself(int vector)
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{
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__default_send_IPI_shortcut(APIC_DEST_ALLBUT, vector);
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}
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void default_send_IPI_all(int vector)
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{
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__default_send_IPI_shortcut(APIC_DEST_ALLINC, vector);
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}
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void default_send_IPI_self(int vector)
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{
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__default_send_IPI_shortcut(APIC_DEST_SELF, vector);
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}
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#ifdef CONFIG_X86_32
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void default_send_IPI_mask_sequence_logical(const struct cpumask *mask,
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int vector)
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{
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unsigned long flags;
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unsigned int query_cpu;
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/*
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* Hack. The clustered APIC addressing mode doesn't allow us to send
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* to an arbitrary mask, so I do a unicasts to each CPU instead. This
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* should be modified to do 1 message per cluster ID - mbligh
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*/
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask)
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__default_send_IPI_dest_field(
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early_per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, apic->dest_logical);
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local_irq_restore(flags);
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}
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void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask,
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int vector)
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{
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unsigned long flags;
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unsigned int query_cpu;
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unsigned int this_cpu = smp_processor_id();
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/* See Hack comment above */
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask) {
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if (query_cpu == this_cpu)
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continue;
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__default_send_IPI_dest_field(
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early_per_cpu(x86_cpu_to_logical_apicid, query_cpu),
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vector, apic->dest_logical);
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}
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local_irq_restore(flags);
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}
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/*
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* This is only used on smaller machines.
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*/
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void default_send_IPI_mask_logical(const struct cpumask *cpumask, int vector)
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{
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unsigned long mask = cpumask_bits(cpumask)[0];
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unsigned long flags;
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if (!mask)
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return;
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local_irq_save(flags);
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WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]);
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__default_send_IPI_dest_field(mask, vector, apic->dest_logical);
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local_irq_restore(flags);
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}
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/* must come after the send_IPI functions above for inlining */
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static int convert_apicid_to_cpu(int apic_id)
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{
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int i;
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for_each_possible_cpu(i) {
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if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
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return i;
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}
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return -1;
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}
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int safe_smp_processor_id(void)
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{
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int apicid, cpuid;
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if (!boot_cpu_has(X86_FEATURE_APIC))
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return 0;
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apicid = hard_smp_processor_id();
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if (apicid == BAD_APICID)
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return 0;
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cpuid = convert_apicid_to_cpu(apicid);
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return cpuid >= 0 ? cpuid : 0;
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}
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#endif
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