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This adds documentation of device tree bindings for the clock related portions of the STM32 RCC block. Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
STMicroelectronics STM32 Reset and Clock Controller
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===================================================
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The RCC IP is both a reset and a clock controller. This documentation only
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describes the clock part.
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Please also refer to clock-bindings.txt in this directory for common clock
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controller binding usage.
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Required properties:
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- compatible: Should be "st,stm32f42xx-rcc"
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- reg: should be register base and length as documented in the
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datasheet
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- #clock-cells: 2, device nodes should specify the clock in their "clocks"
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property, containing a phandle to the clock device node, an index selecting
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between gated clocks and other clocks and an index specifying the clock to
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use.
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Example:
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rcc: rcc@40023800 {
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#clock-cells = <2>
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compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
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reg = <0x40023800 0x400>;
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};
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Specifying gated clocks
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=======================
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The primary index must be set to 0.
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The secondary index is the bit number within the RCC register bank, starting
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from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).
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It is calculated as: index = register_offset / 4 * 32 + bit_offset.
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Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).
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Example:
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/* Gated clock, AHB1 bit 0 (GPIOA) */
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... {
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clocks = <&rcc 0 0>
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};
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/* Gated clock, AHB2 bit 4 (CRYP) */
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... {
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clocks = <&rcc 0 36>
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};
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Specifying other clocks
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=======================
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The primary index must be set to 1.
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The secondary index is bound with the following magic numbers:
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0 SYSTICK
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1 FCLK
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Example:
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/* Misc clock, FCLK */
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... {
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clocks = <&rcc 1 1>
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};
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