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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
e3037485c6
This is a new mac80211 driver for Realtek 802.11ac wireless network chips. rtw88 now supports RTL8822BE/RTL8822CE now, with basic station mode functionalities. The firmware for both can be found at linux-firmware. https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git For RTL8822BE: rtw88/rtw8822b_fw.bin For RTL8822CE: rtw88/rtw8822c_fw.bin And for now, only PCI buses (RTL8xxxE) are supported. We will add support for USB and SDIO in the future. The bus interface abstraction can be seen in this driver such as hci.h. Most of the hardware setting are the same except for some TRX path or probing setup should be separated. Supported: * Basic STA/AP/ADHOC mode, and TDLS (STA is well tested) Missing feature: * WOW/PNO * USB & SDIO bus (such as RTL8xxxU/RTL8xxxS) * BT coexistence (8822B/8822C are combo ICs) * Multiple interfaces (for now single STA is better supported) * Dynamic hardware calibrations (to improve/stabilize performance) Potential problems: * static calibration spends too much time, and it is painful for driver to leave IDLE state. And slows down associate process. But reload function are under development, will be added soon! * TRX statictics misleading, as we are not reporting status correctly, or say, not reporting for "every" packet. The next patch set should have BT coexistence code since RTL8822B/C are combo ICs, and the driver for BT can be found after Linux Kernel v4.20. So it is better to add it first to make WiFi + BT work concurrently. Although now rtw88 is simple but we are developing more features for it. Even we want to add support for more chips such as RTL8821C/RTL8814B. Finally, rtw88 has many authors, listed alphabetically: Ping-Ke Shih <pkshih@realtek.com> Tzu-En Huang <tehuang@realtek.com> Yan-Hsuan Chuang <yhchuang@realtek.com> Reviewed-by: Stanislaw Gruszka <sgruszka@redhat.com> Reviewed-by: Brian Norris <briannorris@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Signed-off-by: Yan-Hsuan Chuang <yhchuang@realtek.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
171 lines
4.2 KiB
C
171 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW8822B_H__
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#define __RTW8822B_H__
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#include <asm/byteorder.h>
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#define RCR_VHT_ACK BIT(26)
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struct rtw8822bu_efuse {
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u8 res4[4]; /* 0xd0 */
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u8 usb_optional_function;
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u8 res5[0x1e];
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u8 res6[2];
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u8 serial[0x0b]; /* 0xf5 */
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u8 vid; /* 0x100 */
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u8 res7;
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u8 pid;
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u8 res8[4];
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u8 mac_addr[ETH_ALEN]; /* 0x107 */
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u8 res9[2];
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u8 vendor_name[0x07];
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u8 res10[2];
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u8 device_name[0x14];
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u8 res11[0xcf];
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u8 package_type; /* 0x1fb */
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u8 res12[0x4];
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};
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struct rtw8822be_efuse {
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u8 mac_addr[ETH_ALEN]; /* 0xd0 */
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u8 vender_id[2];
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u8 device_id[2];
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u8 sub_vender_id[2];
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u8 sub_device_id[2];
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u8 pmc[2];
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u8 exp_device_cap[2];
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u8 msi_cap;
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u8 ltr_cap; /* 0xe3 */
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u8 exp_link_control[2];
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u8 link_cap[4];
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u8 link_control[2];
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u8 serial_number[8];
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u8 res0:2; /* 0xf4 */
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u8 ltr_en:1;
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u8 res1:2;
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u8 obff:2;
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u8 res2:3;
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u8 obff_cap:2;
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u8 res3:4;
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u8 res4[3];
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u8 class_code[3];
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u8 pci_pm_L1_2_supp:1;
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u8 pci_pm_L1_1_supp:1;
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u8 aspm_pm_L1_2_supp:1;
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u8 aspm_pm_L1_1_supp:1;
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u8 L1_pm_substates_supp:1;
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u8 res5:3;
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u8 port_common_mode_restore_time;
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u8 port_t_power_on_scale:2;
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u8 res6:1;
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u8 port_t_power_on_value:5;
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u8 res7;
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};
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struct rtw8822b_efuse {
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__le16 rtl_id;
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u8 res0[0x0e];
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/* power index for four RF paths */
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struct rtw_txpwr_idx txpwr_idx_table[4];
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u8 channel_plan; /* 0xb8 */
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u8 xtal_k;
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u8 thermal_meter;
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u8 iqk_lck;
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u8 pa_type; /* 0xbc */
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u8 lna_type_2g[2]; /* 0xbd */
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u8 lna_type_5g[2];
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u8 rf_board_option;
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u8 rf_feature_option;
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u8 rf_bt_setting;
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u8 eeprom_version;
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u8 eeprom_customer_id;
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u8 tx_bb_swing_setting_2g;
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u8 tx_bb_swing_setting_5g;
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u8 tx_pwr_calibrate_rate;
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u8 rf_antenna_option; /* 0xc9 */
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u8 rfe_option;
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u8 country_code[2];
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u8 res[3];
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union {
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struct rtw8822bu_efuse u;
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struct rtw8822be_efuse e;
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};
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};
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static inline void
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_rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data)
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{
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/* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */
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rtw_write32_mask(rtwdev, addr, mask, data);
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rtw_write32_mask(rtwdev, addr + 0x200, mask, data);
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}
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#define rtw_write32s_mask(rtwdev, addr, mask, data) \
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do { \
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BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \
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\
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_rtw_write32s_mask(rtwdev, addr, mask, data); \
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} while (0)
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/* phy status page0 */
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#define GET_PHY_STAT_P0_PWDB(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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/* phy status page1 */
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#define GET_PHY_STAT_P1_PWDB_A(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
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#define GET_PHY_STAT_P1_PWDB_B(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
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#define GET_PHY_STAT_P1_RF_MODE(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
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#define GET_PHY_STAT_P1_L_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8))
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#define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \
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le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12))
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#define REG_HTSTFWT 0x800
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#define REG_RXPSEL 0x808
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#define BIT_RX_PSEL_RST (BIT(28) | BIT(29))
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#define REG_TXPSEL 0x80c
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#define REG_RXCCAMSK 0x814
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#define REG_CCASEL 0x82c
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#define REG_PDMFTH 0x830
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#define REG_CCA2ND 0x838
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#define REG_L1WT 0x83c
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#define REG_L1PKWT 0x840
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#define REG_MRC 0x850
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#define REG_CLKTRK 0x860
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#define REG_ADCCLK 0x8ac
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#define REG_ADC160 0x8c4
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#define REG_ADC40 0x8c8
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#define REG_CDDTXP 0x93c
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#define REG_TXPSEL1 0x940
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#define REG_ACBB0 0x948
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#define REG_ACBBRXFIR 0x94c
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#define REG_ACGG2TBL 0x958
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#define REG_RXSB 0xa00
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#define REG_ADCINI 0xa04
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#define REG_TXSF2 0xa24
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#define REG_TXSF6 0xa28
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#define REG_RXDESC 0xa2c
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#define REG_ENTXCCK 0xa80
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#define REG_AGCTR_A 0xc08
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#define REG_TXDFIR 0xc20
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#define REG_RXIGI_A 0xc50
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#define REG_TRSW 0xca0
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#define REG_RFESEL0 0xcb0
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#define REG_RFESEL8 0xcb4
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#define REG_RFECTL 0xcb8
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#define REG_RFEINV 0xcbc
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#define REG_AGCTR_B 0xe08
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#define REG_RXIGI_B 0xe50
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#define REG_ANTWT 0x1904
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#define REG_IQKFAILMSK 0x1bf0
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#endif
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