mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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212 lines
7.6 KiB
C
212 lines
7.6 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __NOUVEAU_DMA_H__
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#define __NOUVEAU_DMA_H__
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#include "nouveau_bo.h"
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#include "nouveau_chan.h"
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int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
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void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
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int delta, int length);
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/*
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* There's a hw race condition where you can't jump to your PUT offset,
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* to avoid this we jump to offset + SKIPS and fill the difference with
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* NOPs.
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*
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* xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
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* a SKIPS value of 8. Lets assume that the race condition is to do
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* with writing into the fetch area, we configure a fetch size of 128
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* bytes so we need a larger SKIPS value.
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*/
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#define NOUVEAU_DMA_SKIPS (128 / 4)
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/* Hardcoded object assignments to subchannels (subchannel id). */
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enum {
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NvSubCtxSurf2D = 0,
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NvSubSw = 1,
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NvSubImageBlit = 2,
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NvSub2D = 3,
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NvSubGdiRect = 3,
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NvSubCopy = 4,
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};
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/* Object handles. */
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enum {
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NvM2MF = 0x80000001,
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NvDmaFB = 0x80000002,
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NvDmaTT = 0x80000003,
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NvNotify0 = 0x80000006,
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Nv2D = 0x80000007,
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NvCtxSurf2D = 0x80000008,
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NvRop = 0x80000009,
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NvImagePatt = 0x8000000a,
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NvClipRect = 0x8000000b,
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NvGdiRect = 0x8000000c,
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NvImageBlit = 0x8000000d,
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NvSw = 0x8000000e,
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NvSema = 0x8000000f,
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NvEvoSema0 = 0x80000010,
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NvEvoSema1 = 0x80000011,
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NvNotify1 = 0x80000012,
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/* G80+ display objects */
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NvEvoVRAM = 0x01000000,
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NvEvoFB16 = 0x01000001,
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NvEvoFB32 = 0x01000002,
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NvEvoVRAM_LP = 0x01000003,
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NvEvoSync = 0xcafe0000
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};
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#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
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#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
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#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
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#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
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#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
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#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
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#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
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#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
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#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
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#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
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#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
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#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
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#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
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#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
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#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
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static __must_check inline int
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RING_SPACE(struct nouveau_channel *chan, int size)
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{
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int ret;
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ret = nouveau_dma_wait(chan, 1, size);
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if (ret)
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return ret;
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chan->dma.free -= size;
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return 0;
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}
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static inline void
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OUT_RING(struct nouveau_channel *chan, int data)
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{
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nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
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}
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extern void
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OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);
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static inline void
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BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
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{
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OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
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}
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static inline void
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BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
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{
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OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
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}
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static inline void
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BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
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{
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OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
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}
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static inline void
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BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
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{
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OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
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}
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static inline void
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BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
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{
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OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
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}
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#define WRITE_PUT(val) do { \
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DRM_MEMORYBARRIER(); \
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nouveau_bo_rd32(chan->push.buffer, 0); \
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nv_wo32(chan->object, chan->user_put, ((val) << 2) + chan->push.vma.offset); \
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} while (0)
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static inline void
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FIRE_RING(struct nouveau_channel *chan)
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{
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if (chan->dma.cur == chan->dma.put)
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return;
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chan->accel_done = true;
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if (chan->dma.ib_max) {
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nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2,
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(chan->dma.cur - chan->dma.put) << 2);
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} else {
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WRITE_PUT(chan->dma.cur);
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}
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chan->dma.put = chan->dma.cur;
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}
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static inline void
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WIND_RING(struct nouveau_channel *chan)
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{
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chan->dma.cur = chan->dma.put;
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}
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/* FIFO methods */
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#define NV01_SUBCHAN_OBJECT 0x00000000
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#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
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#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
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#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
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#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
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#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
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#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
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#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
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#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
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#define NV84_SUBCHAN_UEVENT 0x00000020
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#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
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#define NV10_SUBCHAN_REF_CNT 0x00000050
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#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
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#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
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#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
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#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
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#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
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#define NV40_SUBCHAN_YIELD 0x00000080
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/* NV_SW object class */
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#define NV_SW_DMA_VBLSEM 0x0000018c
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#define NV_SW_VBLSEM_OFFSET 0x00000400
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#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
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#define NV_SW_VBLSEM_RELEASE 0x00000408
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#define NV_SW_PAGE_FLIP 0x00000500
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#endif
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