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a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
206 lines
8.0 KiB
C
206 lines
8.0 KiB
C
/*
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* include/asm/dma.h
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*
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* Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _ASM_SPARC64_DMA_H
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#define _ASM_SPARC64_DMA_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <asm/sbus.h>
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#include <asm/delay.h>
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#include <asm/oplib.h>
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/* These are irrelevant for Sparc DMA, but we leave it in so that
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* things can compile.
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*/
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#define MAX_DMA_CHANNELS 8
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#define DMA_MODE_READ 1
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#define DMA_MODE_WRITE 2
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#define MAX_DMA_ADDRESS (~0UL)
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/* Useful constants */
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#define SIZE_16MB (16*1024*1024)
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#define SIZE_64K (64*1024)
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/* SBUS DMA controller reg offsets */
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#define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
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#define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
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#define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
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#define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
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/* DVMA chip revisions */
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enum dvma_rev {
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dvmarev0,
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dvmaesc1,
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dvmarev1,
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dvmarev2,
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dvmarev3,
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dvmarevplus,
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dvmahme
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};
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#define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
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/* Linux DMA information structure, filled during probe. */
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struct sbus_dma {
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struct sbus_dma *next;
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struct sbus_dev *sdev;
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void __iomem *regs;
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/* Status, misc info */
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int node; /* Prom node for this DMA device */
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int running; /* Are we doing DMA now? */
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int allocated; /* Are we "owned" by anyone yet? */
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/* Transfer information. */
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u32 addr; /* Start address of current transfer */
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int nbytes; /* Size of current transfer */
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int realbytes; /* For splitting up large transfers, etc. */
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/* DMA revision */
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enum dvma_rev revision;
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};
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extern struct sbus_dma *dma_chain;
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/* Broken hardware... */
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#define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
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#define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
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/* Main routines in dma.c */
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extern void dvma_init(struct sbus_bus *);
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/* Fields in the cond_reg register */
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/* First, the version identification bits */
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#define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
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#define DMA_VERS0 0x00000000 /* Sunray DMA version */
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#define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
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#define DMA_VERS1 0x80000000 /* DMA rev 1 */
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#define DMA_VERS2 0xa0000000 /* DMA rev 2 */
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#define DMA_VERHME 0xb0000000 /* DMA hme gate array */
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#define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
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#define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
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#define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
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#define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
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#define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
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#define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
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#define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
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#define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
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#define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
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#define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
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#define DMA_ST_WRITE 0x00000100 /* write from device to memory */
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#define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
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#define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
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#define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
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#define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
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#define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
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#define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
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#define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
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#define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
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#define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
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#define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
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#define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
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#define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
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#define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
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#define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
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#define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
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#define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
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#define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
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#define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
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#define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
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#define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
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#define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
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#define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
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#define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
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#define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
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#define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
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#define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
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#define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
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#define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
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#define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
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#define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
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#define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
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/* Values describing the burst-size property from the PROM */
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#define DMA_BURST1 0x01
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#define DMA_BURST2 0x02
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#define DMA_BURST4 0x04
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#define DMA_BURST8 0x08
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#define DMA_BURST16 0x10
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#define DMA_BURST32 0x20
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#define DMA_BURST64 0x40
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#define DMA_BURSTBITS 0x7f
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/* Determine highest possible final transfer address given a base */
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#define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
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/* Yes, I hack a lot of elisp in my spare time... */
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#define DMA_ERROR_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
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#define DMA_IRQ_P(regs) ((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
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#define DMA_WRITE_P(regs) ((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
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#define DMA_OFF(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp &= ~DMA_ENABLE; \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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#define DMA_INTSOFF(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp &= ~DMA_INT_ENAB; \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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#define DMA_INTSON(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp |= DMA_INT_ENAB; \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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#define DMA_PUNTFIFO(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp |= DMA_FIFO_INV; \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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#define DMA_SETSTART(__regs, __addr) \
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sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
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#define DMA_BEGINDMA_W(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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#define DMA_BEGINDMA_R(__regs) \
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do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
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tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
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tmp &= ~DMA_ST_WRITE; \
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sbus_writel(tmp, (__regs) + DMA_CSR); \
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} while(0)
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/* For certain DMA chips, we need to disable ints upon irq entry
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* and turn them back on when we are done. So in any ESP interrupt
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* handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
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* when leaving the handler. You have been warned...
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*/
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#define DMA_IRQ_ENTRY(dma, dregs) do { \
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if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
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} while (0)
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#define DMA_IRQ_EXIT(dma, dregs) do { \
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if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
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} while(0)
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#define for_each_dvma(dma) \
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for((dma) = dma_chain; (dma); (dma) = (dma)->next)
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/* From PCI */
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#ifdef CONFIG_PCI
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extern int isa_dma_bridge_buggy;
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#else
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#define isa_dma_bridge_buggy (0)
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#endif
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#endif /* !(_ASM_SPARC64_DMA_H) */
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