mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 04:50:57 +07:00
247c445c0f
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5. - Additional 32 interrupt support is added w.r.t OMAP4 design. - The AUX CORE boot registers are now made accessible from non-secure SW. - SAR offset are changed and PTMSYNC* registers are removed from SAR. Patch updates the WakeupGen code accordingly. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
61 lines
2.4 KiB
C
61 lines
2.4 KiB
C
/*
|
|
* omap4-sar-layout.h: OMAP4 SAR RAM layout header file
|
|
*
|
|
* Copyright (C) 2011 Texas Instruments, Inc.
|
|
* Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
|
|
#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
|
|
|
|
/*
|
|
* SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
|
|
*/
|
|
#define SAR_BANK1_OFFSET 0x0000
|
|
#define SAR_BANK2_OFFSET 0x1000
|
|
#define SAR_BANK3_OFFSET 0x2000
|
|
#define SAR_BANK4_OFFSET 0x3000
|
|
|
|
/* Scratch pad memory offsets from SAR_BANK1 */
|
|
#define SCU_OFFSET0 0xd00
|
|
#define SCU_OFFSET1 0xd04
|
|
#define OMAP_TYPE_OFFSET 0xd10
|
|
#define L2X0_SAVE_OFFSET0 0xd14
|
|
#define L2X0_SAVE_OFFSET1 0xd18
|
|
#define L2X0_AUXCTRL_OFFSET 0xd1c
|
|
#define L2X0_PREFETCH_CTRL_OFFSET 0xd20
|
|
|
|
/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
|
|
#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET 0xa04
|
|
#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET 0xa08
|
|
|
|
#define SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x500)
|
|
#define SAR_SECURE_RAM_SIZE_OFFSET (SAR_BANK3_OFFSET + 0x504)
|
|
#define SAR_SECRAM_SAVED_AT_OFFSET (SAR_BANK3_OFFSET + 0x508)
|
|
|
|
/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
|
|
#define WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x684)
|
|
#define WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x694)
|
|
#define WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6a4)
|
|
#define WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x6b4)
|
|
#define AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x6c4)
|
|
#define AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x6c8)
|
|
#define PTMSYNCREQ_MASK_OFFSET (SAR_BANK3_OFFSET + 0x6cc)
|
|
#define PTMSYNCREQ_EN_OFFSET (SAR_BANK3_OFFSET + 0x6d0)
|
|
#define SAR_BACKUP_STATUS_WAKEUPGEN 0x10
|
|
|
|
/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
|
|
#define OMAP5_WAKEUPGENENB_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8d4)
|
|
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0 (SAR_BANK3_OFFSET + 0x8e8)
|
|
#define OMAP5_WAKEUPGENENB_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x8fc)
|
|
#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1 (SAR_BANK3_OFFSET + 0x910)
|
|
#define OMAP5_AUXCOREBOOT0_OFFSET (SAR_BANK3_OFFSET + 0x924)
|
|
#define OMAP5_AUXCOREBOOT1_OFFSET (SAR_BANK3_OFFSET + 0x928)
|
|
#define OMAP5_AMBA_IF_MODE_OFFSET (SAR_BANK3_OFFSET + 0x92c)
|
|
#define OMAP5_SAR_BACKUP_STATUS_OFFSET (SAR_BANK3_OFFSET + 0x800)
|
|
|
|
#endif
|