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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e532c06f2a
arch/x86/power/cpu_32.c __save_processor_state calls read_cr4() only a i486 CPU doesn't have the CR4 register. Trying to read it produces an invalid opcode oops during suspend to disk. Use the safe rc4 reading op instead. If the value to be written is zero the write is skipped. arch/x86/power/hibernate_asm_32.S done: swapped the use of %eax and %ecx to use jecxz for the zero test and jump over store to %cr4. restore_image: s/%ecx/%eax/ to be consistent with done: In addition to __save_processor_state, acpi_save_state_mem, efi_call_phys_prelog, and efi_call_phys_epilog had checks added (acpi restore was in assembly and already had a check for non-zero). There were other reads and writes of CR4, but MCE and virtualization shouldn't be executed on a i486 anyway. Signed-off-by: David Fries <david@fries.net> Acked-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
141 lines
2.9 KiB
C
141 lines
2.9 KiB
C
/*
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* Suspend support specific for i386.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/module.h>
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#include <linux/suspend.h>
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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static struct saved_context saved_context;
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unsigned long saved_context_ebx;
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unsigned long saved_context_esp, saved_context_ebp;
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unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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static void __save_processor_state(struct saved_context *ctxt)
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{
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mtrr_save_fixed_ranges(NULL);
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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store_gdt(&ctxt->gdt);
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store_idt(&ctxt->idt);
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store_tr(ctxt->tr);
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/*
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* segment registers
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*/
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savesegment(es, ctxt->es);
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savesegment(fs, ctxt->fs);
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savesegment(gs, ctxt->gs);
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savesegment(ss, ctxt->ss);
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/*
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* control registers
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*/
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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ctxt->cr4 = read_cr4_safe();
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}
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/* Needed by apm.c */
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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EXPORT_SYMBOL(save_processor_state);
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary.
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*/
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kernel_fpu_end();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7) {
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set_debugreg(current->thread.debugreg0, 0);
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set_debugreg(current->thread.debugreg1, 1);
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set_debugreg(current->thread.debugreg2, 2);
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set_debugreg(current->thread.debugreg3, 3);
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/* no 4 and 5 */
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set_debugreg(current->thread.debugreg6, 6);
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set_debugreg(current->thread.debugreg7, 7);
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}
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}
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static void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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load_gdt(&ctxt->gdt);
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load_idt(&ctxt->idt);
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/*
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* segment registers
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*/
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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loadsegment(ss, ctxt->ss);
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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mcheck_init(&boot_cpu_data);
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}
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/* Needed by apm.c */
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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EXPORT_SYMBOL(restore_processor_state);
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