mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 13:42:05 +07:00
d0f58bd3bb
Remove struct dss_clock_info, as it is not usable in a case where DSS fclk comes from a dedicated PLL. Instead, just use the fclk rate in place of dss_clock_info, as that is all that's needed. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
441 lines
13 KiB
C
441 lines
13 KiB
C
/*
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* linux/drivers/video/omap2/dss/dss.h
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*
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* Copyright (C) 2009 Nokia Corporation
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* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
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*
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* Some code and ideas taken from drivers/video/omap/ driver
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* by Imre Deak.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP2_DSS_H
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#define __OMAP2_DSS_H
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#include <linux/interrupt.h>
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#ifdef pr_fmt
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#undef pr_fmt
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
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#else
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#define pr_fmt(fmt) fmt
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#endif
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#define DSSDBG(format, ...) \
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pr_debug(format, ## __VA_ARGS__)
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#ifdef DSS_SUBSYS_NAME
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#define DSSERR(format, ...) \
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printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
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## __VA_ARGS__)
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#else
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#define DSSERR(format, ...) \
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printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSINFO(format, ...) \
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printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
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## __VA_ARGS__)
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#else
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#define DSSINFO(format, ...) \
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printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
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#endif
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#ifdef DSS_SUBSYS_NAME
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#define DSSWARN(format, ...) \
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printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
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## __VA_ARGS__)
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#else
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#define DSSWARN(format, ...) \
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printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
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#endif
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/* OMAP TRM gives bitfields as start:end, where start is the higher bit
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number. For example 7:0 */
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#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
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#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
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#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
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#define FLD_MOD(orig, val, start, end) \
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(((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
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enum dss_io_pad_mode {
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DSS_IO_PAD_MODE_RESET,
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DSS_IO_PAD_MODE_RFBI,
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DSS_IO_PAD_MODE_BYPASS,
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};
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enum dss_hdmi_venc_clk_source_select {
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DSS_VENC_TV_CLK = 0,
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DSS_HDMI_M_PCLK = 1,
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};
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enum dss_dsi_content_type {
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DSS_DSI_CONTENT_DCS,
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DSS_DSI_CONTENT_GENERIC,
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};
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enum dss_writeback_channel {
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DSS_WB_LCD1_MGR = 0,
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DSS_WB_LCD2_MGR = 1,
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DSS_WB_TV_MGR = 2,
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DSS_WB_OVL0 = 3,
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DSS_WB_OVL1 = 4,
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DSS_WB_OVL2 = 5,
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DSS_WB_OVL3 = 6,
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DSS_WB_LCD3_MGR = 7,
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};
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struct dispc_clock_info {
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/* rates that we get with dividers below */
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unsigned long lck;
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unsigned long pck;
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/* dividers */
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u16 lck_div;
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u16 pck_div;
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};
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struct dsi_clock_info {
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/* rates that we get with dividers below */
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unsigned long fint;
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unsigned long clkin4ddr;
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unsigned long clkin;
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unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
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* OMAP4: PLLx_CLK1 */
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unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
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* OMAP4: PLLx_CLK2 */
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unsigned long lp_clk;
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/* dividers */
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u16 regn;
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u16 regm;
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u16 regm_dispc; /* OMAP3: REGM3
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* OMAP4: REGM4 */
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u16 regm_dsi; /* OMAP3: REGM4
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* OMAP4: REGM5 */
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u16 lp_clk_div;
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};
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struct reg_field {
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u16 reg;
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u8 high;
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u8 low;
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};
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struct dss_lcd_mgr_config {
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enum dss_io_pad_mode io_pad_mode;
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bool stallmode;
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bool fifohandcheck;
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struct dispc_clock_info clock_info;
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int video_port_width;
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int lcden_sig_polarity;
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};
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struct seq_file;
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struct platform_device;
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/* core */
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struct platform_device *dss_get_core_pdev(void);
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int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
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void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
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int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
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int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
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/* display */
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int dss_suspend_all_devices(void);
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int dss_resume_all_devices(void);
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void dss_disable_all_devices(void);
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int display_init_sysfs(struct platform_device *pdev);
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void display_uninit_sysfs(struct platform_device *pdev);
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/* manager */
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int dss_init_overlay_managers(void);
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void dss_uninit_overlay_managers(void);
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int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
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void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
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int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
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const struct omap_overlay_manager_info *info);
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int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
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const struct omap_video_timings *timings);
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int dss_mgr_check(struct omap_overlay_manager *mgr,
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struct omap_overlay_manager_info *info,
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const struct omap_video_timings *mgr_timings,
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const struct dss_lcd_mgr_config *config,
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struct omap_overlay_info **overlay_infos);
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static inline bool dss_mgr_is_lcd(enum omap_channel id)
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{
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if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
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id == OMAP_DSS_CHANNEL_LCD3)
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return true;
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else
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return false;
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}
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int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
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struct platform_device *pdev);
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void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
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/* overlay */
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void dss_init_overlays(struct platform_device *pdev);
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void dss_uninit_overlays(struct platform_device *pdev);
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void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
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int dss_ovl_simple_check(struct omap_overlay *ovl,
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const struct omap_overlay_info *info);
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int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
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const struct omap_video_timings *mgr_timings);
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bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
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enum omap_color_mode mode);
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int dss_overlay_kobj_init(struct omap_overlay *ovl,
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struct platform_device *pdev);
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void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
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/* DSS */
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int dss_init_platform_driver(void) __init;
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void dss_uninit_platform_driver(void);
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unsigned long dss_get_dispc_clk_rate(void);
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int dss_dpi_select_source(enum omap_channel channel);
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void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
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enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
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const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
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void dss_dump_clocks(struct seq_file *s);
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#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
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void dss_debug_dump_clocks(struct seq_file *s);
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#endif
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int dss_get_ctx_loss_count(void);
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void dss_sdi_init(int datapairs);
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int dss_sdi_enable(void);
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void dss_sdi_disable(void);
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void dss_select_dsi_clk_source(int dsi_module,
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enum omap_dss_clk_source clk_src);
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void dss_select_lcd_clk_source(enum omap_channel channel,
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enum omap_dss_clk_source clk_src);
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enum omap_dss_clk_source dss_get_dispc_clk_source(void);
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enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
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enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
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void dss_set_venc_output(enum omap_dss_venc_type type);
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void dss_set_dac_pwrdn_bgz(bool enable);
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unsigned long dss_get_dpll4_rate(void);
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int dss_set_fck_rate(unsigned long rate);
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typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
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bool dss_div_calc(unsigned long fck_min, dss_div_calc_func func, void *data);
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/* SDI */
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int sdi_init_platform_driver(void) __init;
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void sdi_uninit_platform_driver(void) __exit;
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/* DSI */
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typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
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unsigned long pll, void *data);
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typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
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void *data);
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#ifdef CONFIG_OMAP2_DSS_DSI
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struct dentry;
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struct file_operations;
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int dsi_init_platform_driver(void) __init;
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void dsi_uninit_platform_driver(void) __exit;
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int dsi_runtime_get(struct platform_device *dsidev);
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void dsi_runtime_put(struct platform_device *dsidev);
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void dsi_dump_clocks(struct seq_file *s);
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void dsi_irq_handler(void);
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u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
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unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
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bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
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unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
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bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dsi_pll_calc_func func, void *data);
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unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
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int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo);
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int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
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bool enable_hsdiv);
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void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
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void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
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void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
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struct platform_device *dsi_get_dsidev_from_id(int module);
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#else
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static inline int dsi_runtime_get(struct platform_device *dsidev)
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{
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return 0;
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}
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static inline void dsi_runtime_put(struct platform_device *dsidev)
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{
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}
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static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
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{
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WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
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return 0;
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}
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static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
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{
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WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
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return 0;
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}
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static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
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struct dsi_clock_info *cinfo)
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{
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WARN("%s: DSI not compiled in\n", __func__);
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return -ENODEV;
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}
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static inline int dsi_pll_init(struct platform_device *dsidev,
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bool enable_hsclk, bool enable_hsdiv)
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{
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WARN("%s: DSI not compiled in\n", __func__);
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return -ENODEV;
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}
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static inline void dsi_pll_uninit(struct platform_device *dsidev,
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bool disconnect_lanes)
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{
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}
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static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
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{
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}
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static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
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{
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}
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static inline struct platform_device *dsi_get_dsidev_from_id(int module)
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{
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return NULL;
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}
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static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
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{
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return 0;
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}
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static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
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unsigned long pll, unsigned long out_min,
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dsi_hsdiv_calc_func func, void *data)
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{
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return false;
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}
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static inline bool dsi_pll_calc(struct platform_device *dsidev,
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unsigned long clkin,
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unsigned long pll_min, unsigned long pll_max,
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dsi_pll_calc_func func, void *data)
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{
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return false;
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}
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#endif
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/* DPI */
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int dpi_init_platform_driver(void) __init;
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void dpi_uninit_platform_driver(void) __exit;
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/* DISPC */
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int dispc_init_platform_driver(void) __init;
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void dispc_uninit_platform_driver(void) __exit;
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void dispc_dump_clocks(struct seq_file *s);
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void dispc_enable_sidle(void);
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void dispc_disable_sidle(void);
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void dispc_lcd_enable_signal(bool enable);
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void dispc_pck_free_enable(bool enable);
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void dispc_enable_fifomerge(bool enable);
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void dispc_enable_gamma_table(bool enable);
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void dispc_set_loadmode(enum omap_dss_load_mode mode);
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typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
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unsigned long pck, void *data);
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bool dispc_div_calc(unsigned long dispc,
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unsigned long pck_min, unsigned long pck_max,
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dispc_div_calc_func func, void *data);
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bool dispc_mgr_timings_ok(enum omap_channel channel,
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const struct omap_video_timings *timings);
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unsigned long dispc_fclk_rate(void);
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int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
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struct dispc_clock_info *cinfo);
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void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
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void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
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u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
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bool manual_update);
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unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
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unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
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unsigned long dispc_core_clk_rate(void);
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void dispc_mgr_set_clock_div(enum omap_channel channel,
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const struct dispc_clock_info *cinfo);
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int dispc_mgr_get_clock_div(enum omap_channel channel,
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struct dispc_clock_info *cinfo);
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void dispc_set_tv_pclk(unsigned long pclk);
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u32 dispc_wb_get_framedone_irq(void);
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bool dispc_wb_go_busy(void);
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void dispc_wb_go(void);
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void dispc_wb_enable(bool enable);
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bool dispc_wb_is_enabled(void);
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void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
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int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
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bool mem_to_mem, const struct omap_video_timings *timings);
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/* VENC */
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int venc_init_platform_driver(void) __init;
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void venc_uninit_platform_driver(void) __exit;
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/* HDMI */
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int hdmi_init_platform_driver(void) __init;
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void hdmi_uninit_platform_driver(void) __exit;
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/* RFBI */
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int rfbi_init_platform_driver(void) __init;
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void rfbi_uninit_platform_driver(void) __exit;
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#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
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static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
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{
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int b;
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for (b = 0; b < 32; ++b) {
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if (irqstatus & (1 << b))
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irq_arr[b]++;
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}
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}
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#endif
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#endif
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