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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9bd43a6184
The clkdev lookup created for the cpufreq device is never removed if there's an issue later in probe or at module removal time. Let's convert to the managed variant of the clk_hw_register_clkdev function to make sure it happens. Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/075e2c6d315eccdaf8fb72b320712b86e6c25b22.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
340 lines
8.6 KiB
C
340 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Raspberry Pi driver for firmware controlled clocks
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*
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* Even though clk-bcm2835 provides an interface to the hardware registers for
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* the system clocks we've had to factor out 'pllb' as the firmware 'owns' it.
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* We're not allowed to change it directly as we might race with the
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* over-temperature and under-voltage protections provided by the firmware.
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*
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* Copyright (C) 2019 Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
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*/
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <soc/bcm2835/raspberrypi-firmware.h>
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#define RPI_FIRMWARE_ARM_CLK_ID 0x00000003
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#define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
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#define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1)
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/*
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* Even though the firmware interface alters 'pllb' the frequencies are
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* provided as per 'pllb_arm'. We need to scale before passing them trough.
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*/
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#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
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#define A2W_PLL_FRAC_BITS 20
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struct raspberrypi_clk {
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struct device *dev;
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struct rpi_firmware *firmware;
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struct platform_device *cpufreq;
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unsigned long min_rate;
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unsigned long max_rate;
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struct clk_hw pllb;
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};
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/*
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* Structure of the message passed to Raspberry Pi's firmware in order to
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* change clock rates. The 'disable_turbo' option is only available to the ARM
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* clock (pllb) which we enable by default as turbo mode will alter multiple
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* clocks at once.
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*
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* Even though we're able to access the clock registers directly we're bound to
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* use the firmware interface as the firmware ultimately takes care of
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* mitigating overheating/undervoltage situations and we would be changing
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* frequencies behind his back.
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*
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* For more information on the firmware interface check:
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* https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface
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*/
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struct raspberrypi_firmware_prop {
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__le32 id;
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__le32 val;
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__le32 disable_turbo;
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} __packed;
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static int raspberrypi_clock_property(struct rpi_firmware *firmware, u32 tag,
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u32 clk, u32 *val)
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{
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struct raspberrypi_firmware_prop msg = {
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.id = cpu_to_le32(clk),
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.val = cpu_to_le32(*val),
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.disable_turbo = cpu_to_le32(1),
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};
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int ret;
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ret = rpi_firmware_property(firmware, tag, &msg, sizeof(msg));
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if (ret)
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return ret;
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*val = le32_to_cpu(msg.val);
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return 0;
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}
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static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
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{
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struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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pllb);
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u32 val = 0;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_CLOCK_STATE,
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RPI_FIRMWARE_ARM_CLK_ID, &val);
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if (ret)
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return 0;
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return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT);
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}
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static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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pllb);
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u32 val = 0;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_CLOCK_RATE,
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RPI_FIRMWARE_ARM_CLK_ID,
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&val);
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if (ret)
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return ret;
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return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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}
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static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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pllb);
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u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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int ret;
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_SET_CLOCK_RATE,
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RPI_FIRMWARE_ARM_CLK_ID,
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&new_rate);
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if (ret)
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dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
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clk_hw_get_name(hw), ret);
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return ret;
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}
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/*
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* Sadly there is no firmware rate rounding interface. We borrowed it from
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* clk-bcm2835.
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*/
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static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
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pllb);
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u64 div, final_rate;
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u32 ndiv, fdiv;
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/* We can't use req->rate directly as it would overflow */
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final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
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div = (u64)final_rate << A2W_PLL_FRAC_BITS;
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do_div(div, req->best_parent_rate);
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ndiv = div >> A2W_PLL_FRAC_BITS;
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fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
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final_rate = ((u64)req->best_parent_rate *
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((ndiv << A2W_PLL_FRAC_BITS) + fdiv));
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req->rate = final_rate >> A2W_PLL_FRAC_BITS;
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return 0;
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}
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static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
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.is_prepared = raspberrypi_fw_pll_is_on,
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.recalc_rate = raspberrypi_fw_pll_get_rate,
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.set_rate = raspberrypi_fw_pll_set_rate,
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.determine_rate = raspberrypi_pll_determine_rate,
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};
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static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
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{
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struct clk_init_data init = {};
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u32 min_rate = 0, max_rate = 0;
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int ret;
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/* All of the PLLs derive from the external oscillator. */
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init.parent_names = (const char *[]){ "osc" };
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init.num_parents = 1;
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init.name = "pllb";
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init.ops = &raspberrypi_firmware_pll_clk_ops;
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init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
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/* Get min & max rates set by the firmware */
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
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RPI_FIRMWARE_ARM_CLK_ID,
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&min_rate);
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if (ret) {
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dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
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init.name, ret);
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return ret;
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}
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ret = raspberrypi_clock_property(rpi->firmware,
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RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
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RPI_FIRMWARE_ARM_CLK_ID,
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&max_rate);
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if (ret) {
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dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
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init.name, ret);
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return ret;
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}
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if (!min_rate || !max_rate) {
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dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
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min_rate, max_rate);
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return -EINVAL;
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}
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dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
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min_rate, max_rate);
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rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
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rpi->pllb.init = &init;
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return devm_clk_hw_register(rpi->dev, &rpi->pllb);
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}
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static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
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.mult = 1,
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.div = 2,
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.hw.init = &(struct clk_init_data) {
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.name = "pllb_arm",
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.parent_names = (const char *[]){ "pllb" },
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.num_parents = 1,
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.ops = &clk_fixed_factor_ops,
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.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
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},
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};
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static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
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{
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int ret;
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ret = devm_clk_hw_register(rpi->dev, &raspberrypi_clk_pllb_arm.hw);
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if (ret) {
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dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
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return ret;
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}
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ret = devm_clk_hw_register_clkdev(rpi->dev,
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&raspberrypi_clk_pllb_arm.hw,
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NULL, "cpu0");
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if (ret) {
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dev_err(rpi->dev, "Failed to initialize clkdev\n");
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return ret;
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}
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return 0;
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}
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static int raspberrypi_clk_probe(struct platform_device *pdev)
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{
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struct device_node *firmware_node;
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struct device *dev = &pdev->dev;
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struct rpi_firmware *firmware;
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struct raspberrypi_clk *rpi;
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int ret;
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/*
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* We can be probed either through the an old-fashioned
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* platform device registration or through a DT node that is a
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* child of the firmware node. Handle both cases.
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*/
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if (dev->of_node)
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firmware_node = of_get_parent(dev->of_node);
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else
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firmware_node = of_find_compatible_node(NULL, NULL,
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"raspberrypi,bcm2835-firmware");
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if (!firmware_node) {
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dev_err(dev, "Missing firmware node\n");
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return -ENOENT;
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}
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firmware = rpi_firmware_get(firmware_node);
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of_node_put(firmware_node);
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if (!firmware)
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return -EPROBE_DEFER;
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rpi = devm_kzalloc(dev, sizeof(*rpi), GFP_KERNEL);
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if (!rpi)
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return -ENOMEM;
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rpi->dev = dev;
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rpi->firmware = firmware;
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platform_set_drvdata(pdev, rpi);
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ret = raspberrypi_register_pllb(rpi);
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if (ret) {
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dev_err(dev, "Failed to initialize pllb, %d\n", ret);
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return ret;
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}
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ret = raspberrypi_register_pllb_arm(rpi);
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if (ret)
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return ret;
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rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",
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-1, NULL, 0);
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return 0;
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}
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static int raspberrypi_clk_remove(struct platform_device *pdev)
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{
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struct raspberrypi_clk *rpi = platform_get_drvdata(pdev);
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platform_device_unregister(rpi->cpufreq);
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return 0;
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}
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static const struct of_device_id raspberrypi_clk_match[] = {
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{ .compatible = "raspberrypi,firmware-clocks" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, raspberrypi_clk_match);
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static struct platform_driver raspberrypi_clk_driver = {
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.driver = {
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.name = "raspberrypi-clk",
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.of_match_table = raspberrypi_clk_match,
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},
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.probe = raspberrypi_clk_probe,
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.remove = raspberrypi_clk_remove,
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};
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module_platform_driver(raspberrypi_clk_driver);
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MODULE_AUTHOR("Nicolas Saenz Julienne <nsaenzjulienne@suse.de>");
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MODULE_DESCRIPTION("Raspberry Pi firmware clock driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:raspberrypi-clk");
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