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Currently, the last stage boot loaders such as U-Boot can accept only uImage which is an unnecessary additional step in automating boot process. Add an image header that boot loader understands and boot Linux from flat Image directly. This header is based on ARM64 boot image header and provides an opportunity to combine both ARM64 & RISC-V image headers in future. Also make sure that PE/COFF header can co-exist in the same image so that EFI stub can be supported for RISC-V in future. EFI specification needs PE/COFF image header in the beginning of the kernel image in order to load it as an EFI application. In order to support EFI stub, code0 should be replaced with "MZ" magic string and res4(at offset 0x3c) should point to the rest of the PE/COFF header (which will be added during EFI support). Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Karsten Merker <merker@debian.org> Tested-by: Karsten Merker <merker@debian.org> (QEMU+OpenSBI+U-Boot) Tested-by: Kevin Hilman <khilman@baylibre.com> (OpenSBI + U-Boot + Linux) [paul.walmsley@sifive.com: fixed whitespace in boot-image-header.txt; converted structure comment to kernel-doc format and added some detail] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
51 lines
2.1 KiB
Plaintext
51 lines
2.1 KiB
Plaintext
Boot image header in RISC-V Linux
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=============================================
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Author: Atish Patra <atish.patra@wdc.com>
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Date : 20 May 2019
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This document only describes the boot image header details for RISC-V Linux.
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The complete booting guide will be available at Documentation/riscv/booting.txt.
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The following 64-byte header is present in decompressed Linux kernel image.
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u32 code0; /* Executable code */
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u32 code1; /* Executable code */
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u64 text_offset; /* Image load offset, little endian */
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u64 image_size; /* Effective Image size, little endian */
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u64 flags; /* kernel flags, little endian */
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u32 version; /* Version of this header */
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u32 res1 = 0; /* Reserved */
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u64 res2 = 0; /* Reserved */
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u64 magic = 0x5643534952; /* Magic number, little endian, "RISCV" */
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u32 res3; /* Reserved for additional RISC-V specific header */
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u32 res4; /* Reserved for PE COFF offset */
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This header format is compliant with PE/COFF header and largely inspired from
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ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
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header in future.
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Notes:
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- This header can also be reused to support EFI stub for RISC-V in future. EFI
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specification needs PE/COFF image header in the beginning of the kernel image
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in order to load it as an EFI application. In order to support EFI stub,
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code0 should be replaced with "MZ" magic string and res5(at offset 0x3c) should
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point to the rest of the PE/COFF header.
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- version field indicate header version number.
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Bits 0:15 - Minor version
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Bits 16:31 - Major version
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This preserves compatibility across newer and older version of the header.
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The current version is defined as 0.1.
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- res3 is reserved for offset to any other additional fields. This makes the
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header extendible in future. One example would be to accommodate ISA
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extension for RISC-V in future. For current version, it is set to be zero.
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- In current header, the flag field has only one field.
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Bit 0: Kernel endianness. 1 if BE, 0 if LE.
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- Image size is mandatory for boot loader to load kernel image. Booting will
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fail otherwise.
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