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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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9274498953
This patch adds support for the Xilinx ll_temac 10/100/1000 Ethernet device. The ll_temac ipcore is typically used on Xilinx Virtex and Spartan designs attached to either a PowerPC 4xx or Microblaze processor. At the present moment, this driver only works with Virtex5 PowerPC designs because it assumes DCR is used to access the DMA registers. However, the low level access to DMA registers is abstracted and it should be easy to adapt for the other implementations. I'm posting this driver now as an RFC. There are still some things that need to be tightened up, but it does appear to be stable. Derived from driver code written by Yoshio Kashiwagi and David H. Lynch Jr. Tested on Xilinx ML507 eval board with Base System Builder generated FPGA design. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/*
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* MDIO bus driver for the Xilinx TEMAC device
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*
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* Copyright (c) 2009 Secret Lab Technologies, Ltd.
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*/
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#include <linux/io.h>
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#include <linux/netdevice.h>
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#include <linux/mutex.h>
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#include <linux/phy.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_mdio.h>
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#include "ll_temac.h"
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/* ---------------------------------------------------------------------
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* MDIO Bus functions
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*/
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static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
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{
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struct temac_local *lp = bus->priv;
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u32 rc;
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/* Write the PHY address to the MIIM Access Initiator register.
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* When the transfer completes, the PHY register value will appear
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* in the LSW0 register */
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mutex_lock(&lp->indirect_mutex);
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temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);
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rc = temac_indirect_in32(lp, XTE_MIIMAI_OFFSET);
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mutex_unlock(&lp->indirect_mutex);
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dev_dbg(lp->dev, "temac_mdio_read(phy_id=%i, reg=%x) == %x\n",
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phy_id, reg, rc);
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return rc;
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}
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static int temac_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
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{
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struct temac_local *lp = bus->priv;
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dev_dbg(lp->dev, "temac_mdio_write(phy_id=%i, reg=%x, val=%x)\n",
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phy_id, reg, val);
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/* First write the desired value into the write data register
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* and then write the address into the access initiator register
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*/
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mutex_lock(&lp->indirect_mutex);
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temac_indirect_out32(lp, XTE_MGTDR_OFFSET, val);
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temac_indirect_out32(lp, XTE_MIIMAI_OFFSET, (phy_id << 5) | reg);
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mutex_unlock(&lp->indirect_mutex);
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return 0;
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}
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int temac_mdio_setup(struct temac_local *lp, struct device_node *np)
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{
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struct mii_bus *bus;
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const u32 *bus_hz;
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int clk_div;
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int rc, size;
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struct resource res;
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/* Calculate a reasonable divisor for the clock rate */
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clk_div = 0x3f; /* worst-case default setting */
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bus_hz = of_get_property(np, "clock-frequency", &size);
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if (bus_hz && size >= sizeof(*bus_hz)) {
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clk_div = (*bus_hz) / (2500 * 1000 * 2) - 1;
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if (clk_div < 1)
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clk_div = 1;
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if (clk_div > 0x3f)
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clk_div = 0x3f;
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}
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/* Enable the MDIO bus by asserting the enable bit and writing
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* in the clock config */
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mutex_lock(&lp->indirect_mutex);
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temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);
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mutex_unlock(&lp->indirect_mutex);
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bus = mdiobus_alloc();
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if (!bus)
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return -ENOMEM;
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of_address_to_resource(np, 0, &res);
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snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
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(unsigned long long)res.start);
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bus->priv = lp;
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bus->name = "Xilinx TEMAC MDIO";
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bus->read = temac_mdio_read;
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bus->write = temac_mdio_write;
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bus->parent = lp->dev;
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bus->irq = lp->mdio_irqs; /* preallocated IRQ table */
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lp->mii_bus = bus;
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rc = of_mdiobus_register(bus, np);
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if (rc)
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goto err_register;
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mutex_lock(&lp->indirect_mutex);
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dev_dbg(lp->dev, "MDIO bus registered; MC:%x\n",
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temac_indirect_in32(lp, XTE_MC_OFFSET));
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mutex_unlock(&lp->indirect_mutex);
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return 0;
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err_register:
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mdiobus_free(bus);
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return rc;
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}
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void temac_mdio_teardown(struct temac_local *lp)
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{
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mdiobus_unregister(lp->mii_bus);
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kfree(lp->mii_bus->irq);
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mdiobus_free(lp->mii_bus);
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lp->mii_bus = NULL;
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}
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