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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1228c051ba
This contains a couple of fixes to existing device trees, enables CPU frequency scaling on various Tegra210 boards, enables the TCU as debug serial port on Jetson Xavier, adds various improvements for SDMMC on Tegra210, Tegra186 and Tegra194 boards and finally adds initial support for the NVIDIA Shield TV. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAlxdmX0THHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zob8+D/4oX6rlHS70H1CVhEF/2JejVBki5iX2 YGsjtywFGVU072OjQrIXARq/7LlH/4ykF8m8rNCTCzL1SewxpAhzTuyHSAitREjX FMICa9bfv26J8n4n9SVOvuWmHc88rK3xaXgiKXIO/2viZsVDC7jeEfl/ztbSUWC7 KHx3moU3mzM0AqIX0z+tYg93uxYpx/sUgygLsJIneaj7b1g5sMZCAdLWQnvXmZKf q5WTwbfUmhg2OrhnO6WXr6swmo7cXKO3zJcm/+b2adf01axMgCjA1RVFgO9yonqn s2402oVRv/y7jsM7HGptlS6NqcurMnhlKCEUsVucXugWwbbAj/oFirYiCWW6fkq/ fgpOVbudjtF4jEiwxJ1KOVXlT34/Tt/Rksxr9uAht2L3KyDCT6mVKFVHq2jIFYVx bIXT9HB3/ZjoVQzQKwRqKR8P9923avMmGvkGrDVXvvXx10hm7CK+UYJxOuwf80dQ 7ahfqSf34Pm3ezWpzr2TJxbd1DOFl57W2K/BjM3eUolwYXwIv8jANj87CqJj+llf gtzMZS1bEdmFiP8DVnW0oQRS7quqSw0jo6qYLPV/dUBMPLFN8kdoWC9AfpQAaOxY jJjpKBTkRcpc48TNAqcAuq53d1f+fsRptuIX2sLuSz7i3mQ80fJo+dET836Q0nYx YYgVNWlJ5FTYyg== =31KA -----END PGP SIGNATURE----- Merge tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt arm64: tegra: Device tree changes for v5.1-rc1 This contains a couple of fixes to existing device trees, enables CPU frequency scaling on various Tegra210 boards, enables the TCU as debug serial port on Jetson Xavier, adds various improvements for SDMMC on Tegra210, Tegra186 and Tegra194 boards and finally adds initial support for the NVIDIA Shield TV. * tag 'tegra-for-5.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (25 commits) arm64: tegra: Update compatible for Tegra186 I2C arm64: tegra: Update compatible for Tegra210 I2C arm64: tegra: Support 200 MHz for SDMMC on Tegra194 arm64: tegra: Add CQE Support for SDMMC4 arm64: tegra: Add SDMMC auto-calibration settings arm64: tegra: Mark TCU as primary serial port on Tegra194 P2888 arm64: tegra: Add nodes for TCU on Tegra194 arm64: tegra: Enable DFLL clock on Smaug arm64: tegra: Add CPU power rail regulator on Smaug arm64: tegra: Enable DFLL clock on Jetson TX1 arm64: tegra: Add pinmux for PWM-based DFLL support on P2597 arm64: tegra: Add CPU clocks on Tegra210 arm64: tegra: Add DFLL clock on Tegra210 arm64: tegra: p2771-0000: Use TEGRA186_ prefix for GPIO names arm64: tegra: p3310: Use TEGRA186_ prefix for GPIO names arm64: tegra: p2597: Sort nodes by unit-address arm64: tegra: p2972: Sort nodes properly arm64: tegra: Add regulators for Tegra210 Darcy arm64: tegra: Add pinmux for Darcy board arm64: tegra: Add gpio-keys nodes for Darcy ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
1058 lines
29 KiB
Plaintext
1058 lines
29 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/clock/tegra194-clock.h>
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#include <dt-bindings/gpio/tegra194-gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/mailbox/tegra186-hsp.h>
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#include <dt-bindings/reset/tegra194-reset.h>
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#include <dt-bindings/power/tegra194-powergate.h>
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#include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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/ {
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compatible = "nvidia,tegra194";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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/* control backbone */
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cbb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x40000000>;
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gpio: gpio@2200000 {
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compatible = "nvidia,tegra194-gpio";
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reg-names = "security", "gpio";
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reg = <0x2200000 0x10000>,
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<0x2210000 0x10000>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <2>;
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interrupt-controller;
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#gpio-cells = <2>;
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gpio-controller;
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};
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ethernet@2490000 {
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compatible = "nvidia,tegra186-eqos",
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"snps,dwc-qos-ethernet-4.10";
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reg = <0x02490000 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
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<&bpmp TEGRA194_CLK_EQOS_AXI>,
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<&bpmp TEGRA194_CLK_EQOS_RX>,
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<&bpmp TEGRA194_CLK_EQOS_TX>,
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<&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
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clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
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resets = <&bpmp TEGRA194_RESET_EQOS>;
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reset-names = "eqos";
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status = "disabled";
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snps,write-requests = <1>;
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snps,read-requests = <3>;
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snps,burst-map = <0x7>;
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snps,txpbl = <16>;
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snps,rxpbl = <8>;
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};
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uarta: serial@3100000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03100000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTA>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTA>;
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reset-names = "serial";
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status = "disabled";
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};
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uartb: serial@3110000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03110000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTB>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTB>;
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reset-names = "serial";
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status = "disabled";
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};
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uartd: serial@3130000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03130000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTD>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTD>;
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reset-names = "serial";
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status = "disabled";
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};
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uarte: serial@3140000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03140000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTE>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTE>;
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reset-names = "serial";
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status = "disabled";
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};
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uartf: serial@3150000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03150000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTF>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTF>;
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reset-names = "serial";
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status = "disabled";
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};
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gen1_i2c: i2c@3160000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03160000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C1>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C1>;
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reset-names = "i2c";
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status = "disabled";
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};
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uarth: serial@3170000 {
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compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
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reg = <0x03170000 0x40>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_UARTH>;
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clock-names = "serial";
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resets = <&bpmp TEGRA194_RESET_UARTH>;
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reset-names = "serial";
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status = "disabled";
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};
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cam_i2c: i2c@3180000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03180000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C3>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C3>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux1 */
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dp_aux_ch1_i2c: i2c@3190000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x03190000 0x10000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C4>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C4>;
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reset-names = "i2c";
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status = "disabled";
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};
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/* shares pads with dpaux0 */
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dp_aux_ch0_i2c: i2c@31b0000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031b0000 0x10000>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C6>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C6>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen7_i2c: i2c@31c0000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031c0000 0x10000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C7>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C7>;
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reset-names = "i2c";
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status = "disabled";
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};
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gen9_i2c: i2c@31e0000 {
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compatible = "nvidia,tegra194-i2c";
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reg = <0x031e0000 0x10000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&bpmp TEGRA194_CLK_I2C9>;
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clock-names = "div-clk";
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resets = <&bpmp TEGRA194_RESET_I2C9>;
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reset-names = "i2c";
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status = "disabled";
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};
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pwm1: pwm@3280000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x3280000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM1>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM1>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm2: pwm@3290000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x3290000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM2>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM2>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm3: pwm@32a0000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x32a0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM3>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM3>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm5: pwm@32c0000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x32c0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM5>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM5>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm6: pwm@32d0000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x32d0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM6>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM6>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm7: pwm@32e0000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x32e0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM7>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM7>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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pwm8: pwm@32f0000 {
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compatible = "nvidia,tegra194-pwm",
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"nvidia,tegra186-pwm";
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reg = <0x32f0000 0x10000>;
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clocks = <&bpmp TEGRA194_CLK_PWM8>;
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clock-names = "pwm";
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resets = <&bpmp TEGRA194_RESET_PWM8>;
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reset-names = "pwm";
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status = "disabled";
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#pwm-cells = <2>;
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};
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sdmmc1: sdhci@3400000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03400000 0x10000>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA194_RESET_SDMMC1>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-3v3-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
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nvidia,default-tap = <0x9>;
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nvidia,default-trim = <0x5>;
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status = "disabled";
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};
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sdmmc3: sdhci@3440000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03440000 0x10000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
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clock-names = "sdhci";
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resets = <&bpmp TEGRA194_RESET_SDMMC3>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout =
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<0x07>;
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nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
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nvidia,default-tap = <0x9>;
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nvidia,default-trim = <0x5>;
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status = "disabled";
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};
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sdmmc4: sdhci@3460000 {
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compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
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reg = <0x03460000 0x10000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
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clock-names = "sdhci";
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assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
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<&bpmp TEGRA194_CLK_PLLC4>;
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assigned-clock-parents =
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<&bpmp TEGRA194_CLK_PLLC4>;
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resets = <&bpmp TEGRA194_RESET_SDMMC4>;
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reset-names = "sdhci";
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nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
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nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
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nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
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nvidia,pad-autocal-pull-down-offset-1v8-timeout =
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<0x0a>;
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nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
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nvidia,pad-autocal-pull-down-offset-3v3-timeout =
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<0x0a>;
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nvidia,default-tap = <0x8>;
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|
nvidia,default-trim = <0x14>;
|
|
nvidia,dqs-trim = <40>;
|
|
supports-cqe;
|
|
status = "disabled";
|
|
};
|
|
|
|
hda@3510000 {
|
|
compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
|
|
reg = <0x3510000 0x10000>;
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_HDA>,
|
|
<&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
|
|
<&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
|
|
clock-names = "hda", "hda2codec_2x", "hda2hdmi";
|
|
resets = <&bpmp TEGRA194_RESET_HDA>,
|
|
<&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
|
|
<&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
|
|
reset-names = "hda", "hda2codec_2x", "hda2hdmi";
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@3881000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
reg = <0x03881000 0x1000>,
|
|
<0x03882000 0x2000>,
|
|
<0x03884000 0x2000>,
|
|
<0x03886000 0x2000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
cec@3960000 {
|
|
compatible = "nvidia,tegra194-cec";
|
|
reg = <0x03960000 0x10000>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_CEC>;
|
|
clock-names = "cec";
|
|
status = "disabled";
|
|
};
|
|
|
|
hsp_top0: hsp@3c00000 {
|
|
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
|
|
reg = <0x03c00000 0xa0000>;
|
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "doorbell", "shared0", "shared1", "shared2",
|
|
"shared3", "shared4", "shared5", "shared6",
|
|
"shared7";
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
hsp_aon: hsp@c150000 {
|
|
compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
|
|
reg = <0x0c150000 0xa0000>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
/*
|
|
* Shared interrupt 0 is routed only to AON/SPE, so
|
|
* we only have 4 shared interrupts for the CCPLEX.
|
|
*/
|
|
interrupt-names = "shared1", "shared2", "shared3", "shared4";
|
|
#mbox-cells = <2>;
|
|
};
|
|
|
|
gen2_i2c: i2c@c240000 {
|
|
compatible = "nvidia,tegra194-i2c";
|
|
reg = <0x0c240000 0x10000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&bpmp TEGRA194_CLK_I2C2>;
|
|
clock-names = "div-clk";
|
|
resets = <&bpmp TEGRA194_RESET_I2C2>;
|
|
reset-names = "i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
gen8_i2c: i2c@c250000 {
|
|
compatible = "nvidia,tegra194-i2c";
|
|
reg = <0x0c250000 0x10000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&bpmp TEGRA194_CLK_I2C8>;
|
|
clock-names = "div-clk";
|
|
resets = <&bpmp TEGRA194_RESET_I2C8>;
|
|
reset-names = "i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@c280000 {
|
|
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0c280000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_UARTC>;
|
|
clock-names = "serial";
|
|
resets = <&bpmp TEGRA194_RESET_UARTC>;
|
|
reset-names = "serial";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartg: serial@c290000 {
|
|
compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
|
|
reg = <0x0c290000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_UARTG>;
|
|
clock-names = "serial";
|
|
resets = <&bpmp TEGRA194_RESET_UARTG>;
|
|
reset-names = "serial";
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@c2a0000 {
|
|
compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
|
|
reg = <0x0c2a0000 0x10000>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
|
|
clock-names = "rtc";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio_aon: gpio@c2f0000 {
|
|
compatible = "nvidia,tegra194-gpio-aon";
|
|
reg-names = "security", "gpio";
|
|
reg = <0xc2f0000 0x1000>,
|
|
<0xc2f1000 0x1000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pwm4: pwm@c340000 {
|
|
compatible = "nvidia,tegra194-pwm",
|
|
"nvidia,tegra186-pwm";
|
|
reg = <0xc340000 0x10000>;
|
|
clocks = <&bpmp TEGRA194_CLK_PWM4>;
|
|
clock-names = "pwm";
|
|
resets = <&bpmp TEGRA194_RESET_PWM4>;
|
|
reset-names = "pwm";
|
|
status = "disabled";
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
pmc: pmc@c360000 {
|
|
compatible = "nvidia,tegra194-pmc";
|
|
reg = <0x0c360000 0x10000>,
|
|
<0x0c370000 0x10000>,
|
|
<0x0c380000 0x10000>,
|
|
<0x0c390000 0x10000>,
|
|
<0x0c3a0000 0x10000>;
|
|
reg-names = "pmc", "wake", "aotag", "scratch", "misc";
|
|
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
host1x@13e00000 {
|
|
compatible = "nvidia,tegra194-host1x", "simple-bus";
|
|
reg = <0x13e00000 0x10000>,
|
|
<0x13e10000 0x10000>;
|
|
reg-names = "hypervisor", "vm";
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_HOST1X>;
|
|
clock-names = "host1x";
|
|
resets = <&bpmp TEGRA194_RESET_HOST1X>;
|
|
reset-names = "host1x";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x15000000 0x15000000 0x01000000>;
|
|
|
|
display-hub@15200000 {
|
|
compatible = "nvidia,tegra194-display", "simple-bus";
|
|
reg = <0x15200000 0x00040000>;
|
|
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
|
|
<&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
|
|
reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
|
|
"wgrp3", "wgrp4", "wgrp5";
|
|
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
|
|
<&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
|
|
clock-names = "disp", "hub";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x15200000 0x15200000 0x40000>;
|
|
|
|
display@15200000 {
|
|
compatible = "nvidia,tegra194-dc";
|
|
reg = <0x15200000 0x10000>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
|
|
clock-names = "dc";
|
|
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
|
|
reset-names = "dc";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
|
|
nvidia,head = <0>;
|
|
};
|
|
|
|
display@15210000 {
|
|
compatible = "nvidia,tegra194-dc";
|
|
reg = <0x15210000 0x10000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
|
|
clock-names = "dc";
|
|
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
|
|
reset-names = "dc";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
|
|
|
|
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
|
|
nvidia,head = <1>;
|
|
};
|
|
|
|
display@15220000 {
|
|
compatible = "nvidia,tegra194-dc";
|
|
reg = <0x15220000 0x10000>;
|
|
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
|
|
clock-names = "dc";
|
|
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
|
|
reset-names = "dc";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
|
|
|
|
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
|
|
nvidia,head = <2>;
|
|
};
|
|
|
|
display@15230000 {
|
|
compatible = "nvidia,tegra194-dc";
|
|
reg = <0x15230000 0x10000>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
|
|
clock-names = "dc";
|
|
resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
|
|
reset-names = "dc";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
|
|
|
|
nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
|
|
nvidia,head = <3>;
|
|
};
|
|
};
|
|
|
|
vic@15340000 {
|
|
compatible = "nvidia,tegra194-vic";
|
|
reg = <0x15340000 0x00040000>;
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_VIC>;
|
|
clock-names = "vic";
|
|
resets = <&bpmp TEGRA194_RESET_VIC>;
|
|
reset-names = "vic";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
|
|
};
|
|
|
|
dpaux0: dpaux@155c0000 {
|
|
compatible = "nvidia,tegra194-dpaux";
|
|
reg = <0x155c0000 0x10000>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_DPAUX>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>;
|
|
clock-names = "dpaux", "parent";
|
|
resets = <&bpmp TEGRA194_RESET_DPAUX>;
|
|
reset-names = "dpaux";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
state_dpaux0_aux: pinmux-aux {
|
|
groups = "dpaux-io";
|
|
function = "aux";
|
|
};
|
|
|
|
state_dpaux0_i2c: pinmux-i2c {
|
|
groups = "dpaux-io";
|
|
function = "i2c";
|
|
};
|
|
|
|
state_dpaux0_off: pinmux-off {
|
|
groups = "dpaux-io";
|
|
function = "off";
|
|
};
|
|
|
|
i2c-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
dpaux1: dpaux@155d0000 {
|
|
compatible = "nvidia,tegra194-dpaux";
|
|
reg = <0x155d0000 0x10000>;
|
|
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>;
|
|
clock-names = "dpaux", "parent";
|
|
resets = <&bpmp TEGRA194_RESET_DPAUX1>;
|
|
reset-names = "dpaux";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
state_dpaux1_aux: pinmux-aux {
|
|
groups = "dpaux-io";
|
|
function = "aux";
|
|
};
|
|
|
|
state_dpaux1_i2c: pinmux-i2c {
|
|
groups = "dpaux-io";
|
|
function = "i2c";
|
|
};
|
|
|
|
state_dpaux1_off: pinmux-off {
|
|
groups = "dpaux-io";
|
|
function = "off";
|
|
};
|
|
|
|
i2c-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
dpaux2: dpaux@155e0000 {
|
|
compatible = "nvidia,tegra194-dpaux";
|
|
reg = <0x155e0000 0x10000>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>;
|
|
clock-names = "dpaux", "parent";
|
|
resets = <&bpmp TEGRA194_RESET_DPAUX2>;
|
|
reset-names = "dpaux";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
state_dpaux2_aux: pinmux-aux {
|
|
groups = "dpaux-io";
|
|
function = "aux";
|
|
};
|
|
|
|
state_dpaux2_i2c: pinmux-i2c {
|
|
groups = "dpaux-io";
|
|
function = "i2c";
|
|
};
|
|
|
|
state_dpaux2_off: pinmux-off {
|
|
groups = "dpaux-io";
|
|
function = "off";
|
|
};
|
|
|
|
i2c-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
dpaux3: dpaux@155f0000 {
|
|
compatible = "nvidia,tegra194-dpaux";
|
|
reg = <0x155f0000 0x10000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>;
|
|
clock-names = "dpaux", "parent";
|
|
resets = <&bpmp TEGRA194_RESET_DPAUX3>;
|
|
reset-names = "dpaux";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
|
|
state_dpaux3_aux: pinmux-aux {
|
|
groups = "dpaux-io";
|
|
function = "aux";
|
|
};
|
|
|
|
state_dpaux3_i2c: pinmux-i2c {
|
|
groups = "dpaux-io";
|
|
function = "i2c";
|
|
};
|
|
|
|
state_dpaux3_off: pinmux-off {
|
|
groups = "dpaux-io";
|
|
function = "off";
|
|
};
|
|
|
|
i2c-bus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
|
|
sor0: sor@15b00000 {
|
|
compatible = "nvidia,tegra194-sor";
|
|
reg = <0x15b00000 0x40000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
|
|
<&bpmp TEGRA194_CLK_SOR0_OUT>,
|
|
<&bpmp TEGRA194_CLK_PLLD>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>,
|
|
<&bpmp TEGRA194_CLK_SOR_SAFE>,
|
|
<&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
|
|
clock-names = "sor", "out", "parent", "dp", "safe",
|
|
"pad";
|
|
resets = <&bpmp TEGRA194_RESET_SOR0>;
|
|
reset-names = "sor";
|
|
pinctrl-0 = <&state_dpaux0_aux>;
|
|
pinctrl-1 = <&state_dpaux0_i2c>;
|
|
pinctrl-2 = <&state_dpaux0_off>;
|
|
pinctrl-names = "aux", "i2c", "off";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
nvidia,interface = <0>;
|
|
};
|
|
|
|
sor1: sor@15b40000 {
|
|
compatible = "nvidia,tegra194-sor";
|
|
reg = <0x155c0000 0x40000>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
|
|
<&bpmp TEGRA194_CLK_SOR1_OUT>,
|
|
<&bpmp TEGRA194_CLK_PLLD2>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>,
|
|
<&bpmp TEGRA194_CLK_SOR_SAFE>,
|
|
<&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
|
|
clock-names = "sor", "out", "parent", "dp", "safe",
|
|
"pad";
|
|
resets = <&bpmp TEGRA194_RESET_SOR1>;
|
|
reset-names = "sor";
|
|
pinctrl-0 = <&state_dpaux1_aux>;
|
|
pinctrl-1 = <&state_dpaux1_i2c>;
|
|
pinctrl-2 = <&state_dpaux1_off>;
|
|
pinctrl-names = "aux", "i2c", "off";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
nvidia,interface = <1>;
|
|
};
|
|
|
|
sor2: sor@15b80000 {
|
|
compatible = "nvidia,tegra194-sor";
|
|
reg = <0x15b80000 0x40000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
|
|
<&bpmp TEGRA194_CLK_SOR2_OUT>,
|
|
<&bpmp TEGRA194_CLK_PLLD3>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>,
|
|
<&bpmp TEGRA194_CLK_SOR_SAFE>,
|
|
<&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
|
|
clock-names = "sor", "out", "parent", "dp", "safe",
|
|
"pad";
|
|
resets = <&bpmp TEGRA194_RESET_SOR2>;
|
|
reset-names = "sor";
|
|
pinctrl-0 = <&state_dpaux2_aux>;
|
|
pinctrl-1 = <&state_dpaux2_i2c>;
|
|
pinctrl-2 = <&state_dpaux2_off>;
|
|
pinctrl-names = "aux", "i2c", "off";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
nvidia,interface = <2>;
|
|
};
|
|
|
|
sor3: sor@15bc0000 {
|
|
compatible = "nvidia,tegra194-sor";
|
|
reg = <0x15bc0000 0x40000>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
|
|
<&bpmp TEGRA194_CLK_SOR3_OUT>,
|
|
<&bpmp TEGRA194_CLK_PLLD4>,
|
|
<&bpmp TEGRA194_CLK_PLLDP>,
|
|
<&bpmp TEGRA194_CLK_SOR_SAFE>,
|
|
<&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
|
|
clock-names = "sor", "out", "parent", "dp", "safe",
|
|
"pad";
|
|
resets = <&bpmp TEGRA194_RESET_SOR3>;
|
|
reset-names = "sor";
|
|
pinctrl-0 = <&state_dpaux3_aux>;
|
|
pinctrl-1 = <&state_dpaux3_i2c>;
|
|
pinctrl-2 = <&state_dpaux3_off>;
|
|
pinctrl-names = "aux", "i2c", "off";
|
|
status = "disabled";
|
|
|
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
|
|
nvidia,interface = <3>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sysram@40000000 {
|
|
compatible = "nvidia,tegra194-sysram", "mmio-sram";
|
|
reg = <0x0 0x40000000 0x0 0x50000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x40000000 0x50000>;
|
|
|
|
cpu_bpmp_tx: shmem@4e000 {
|
|
compatible = "nvidia,tegra194-bpmp-shmem";
|
|
reg = <0x4e000 0x1000>;
|
|
label = "cpu-bpmp-tx";
|
|
pool;
|
|
};
|
|
|
|
cpu_bpmp_rx: shmem@4f000 {
|
|
compatible = "nvidia,tegra194-bpmp-shmem";
|
|
reg = <0x4f000 0x1000>;
|
|
label = "cpu-bpmp-rx";
|
|
pool;
|
|
};
|
|
};
|
|
|
|
bpmp: bpmp {
|
|
compatible = "nvidia,tegra186-bpmp";
|
|
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
|
|
TEGRA_HSP_DB_MASTER_BPMP>;
|
|
shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
#power-domain-cells = <1>;
|
|
|
|
bpmp_i2c: i2c {
|
|
compatible = "nvidia,tegra186-bpmp-i2c";
|
|
nvidia,bpmp-bus-id = <5>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
bpmp_thermal: thermal {
|
|
compatible = "nvidia,tegra186-bpmp-thermal";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x10000>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x10001>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@2 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x100>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@3 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x101>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@4 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x200>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@5 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x201>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@6 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x10300>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
cpu@7 {
|
|
compatible = "nvidia,tegra194-carmel";
|
|
device_type = "cpu";
|
|
reg = <0x10301>;
|
|
enable-method = "psci";
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
status = "okay";
|
|
method = "smc";
|
|
};
|
|
|
|
tcu: tcu {
|
|
compatible = "nvidia,tegra194-tcu";
|
|
mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
|
|
<&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
|
|
mbox-names = "rx", "tx";
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_CPU>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpu {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_GPU>;
|
|
status = "disabled";
|
|
};
|
|
|
|
aux {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_AUX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pllx {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ao {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_AO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tj {
|
|
thermal-sensors = <&{/bpmp/thermal}
|
|
TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
};
|