Nicholas Piggin 9b81c0211c powerpc/64s: make PACA_IRQ_HARD_DIS track MSR[EE] closely ... When the masked interrupt handler clears MSR[EE] for an interrupt in the PACA_IRQ_MUST_HARD_MASK set, it does not set PACA_IRQ_HARD_DIS. This makes them get out of synch. With that taken into account, it's only low level irq manipulation (and interrupt entry before reconcile) where they can be out of synch. This makes the code less surprising. It also allows the IRQ replay code to rely on the IRQ_HARD_DIS value and not have to mtmsrd again in this case (e.g., for an external interrupt that has been masked). The bigger benefit might just be that there is not such an element of surprise in these two bits of state. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2018-07-24 22:03:14 +10:00
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asm	powerpc/64s: make PACA_IRQ_HARD_DIS track MSR[EE] closely	2018-07-24 22:03:14 +10:00
uapi/asm	powerpc: Wire up io_pgetevents	2018-06-23 21:43:21 +10:00