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5bf5dbeda2
ENDPTFLUSH and ENDPTPRIME registers are set by software and clear by hardware. There is a bit for each endpoint. When we are setting a bit for an endpoint we should make sure we do not touch other endpoint bit. There is a race condition if the hardware clear the bit between the read and the write in hw_write. Cc: stable <stable@vger.kernel.org> # 3.11+ Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Matthieu CASTET <matthieu.castet@parrot.com> Tested-by: Michael Grzeschik <mgrzeschik@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
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| .. | ||
| bits.h | ||
| ci_hdrc_imx.c | ||
| ci_hdrc_imx.h | ||
| ci_hdrc_msm.c | ||
| ci_hdrc_pci.c | ||
| ci.h | ||
| core.c | ||
| debug.c | ||
| debug.h | ||
| host.c | ||
| host.h | ||
| Kconfig | ||
| Makefile | ||
| otg.c | ||
| otg.h | ||
| udc.c | ||
| udc.h | ||
| usbmisc_imx.c | ||