mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 15:20:37 +07:00
221e00d1fc
Add explicit RETs to the tail calls of AEGIS and MORUS crypto algorithms
otherwise they run into INT3 padding due to
("x86/asm: Pad assembly functions with INT3 instructions")
leading to spurious debug exceptions.
Mike Galbraith <efault@gmx.de> took care of all the remaining callsites.
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Ondrej Mosnacek <omosnacek@gmail.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
704 lines
10 KiB
ArmAsm
704 lines
10 KiB
ArmAsm
/*
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* AES-NI + SSE2 implementation of AEGIS-128L
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*
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* Copyright (c) 2017-2018 Ondrej Mosnacek <omosnacek@gmail.com>
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* Copyright (C) 2017-2018 Red Hat, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/frame.h>
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#define STATE0 %xmm0
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#define STATE1 %xmm1
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#define STATE2 %xmm2
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#define STATE3 %xmm3
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#define STATE4 %xmm4
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#define STATE5 %xmm5
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#define MSG %xmm6
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#define T0 %xmm7
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#define T1 %xmm8
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#define T2 %xmm9
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#define T3 %xmm10
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#define STATEP %rdi
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#define LEN %rsi
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#define SRC %rdx
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#define DST %rcx
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.section .rodata.cst16.aegis256_const, "aM", @progbits, 32
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.align 16
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.Laegis256_const_0:
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.byte 0x00, 0x01, 0x01, 0x02, 0x03, 0x05, 0x08, 0x0d
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.byte 0x15, 0x22, 0x37, 0x59, 0x90, 0xe9, 0x79, 0x62
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.Laegis256_const_1:
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.byte 0xdb, 0x3d, 0x18, 0x55, 0x6d, 0xc2, 0x2f, 0xf1
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.byte 0x20, 0x11, 0x31, 0x42, 0x73, 0xb5, 0x28, 0xdd
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.section .rodata.cst16.aegis256_counter, "aM", @progbits, 16
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.align 16
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.Laegis256_counter:
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.byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
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.byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f
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.text
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/*
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* __load_partial: internal ABI
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* input:
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* LEN - bytes
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* SRC - src
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* output:
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* MSG - message block
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* changed:
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* T0
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* %r8
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* %r9
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*/
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__load_partial:
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xor %r9, %r9
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pxor MSG, MSG
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mov LEN, %r8
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and $0x1, %r8
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jz .Lld_partial_1
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mov LEN, %r8
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and $0x1E, %r8
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add SRC, %r8
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mov (%r8), %r9b
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.Lld_partial_1:
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mov LEN, %r8
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and $0x2, %r8
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jz .Lld_partial_2
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mov LEN, %r8
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and $0x1C, %r8
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add SRC, %r8
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shl $0x10, %r9
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mov (%r8), %r9w
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.Lld_partial_2:
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mov LEN, %r8
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and $0x4, %r8
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jz .Lld_partial_4
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mov LEN, %r8
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and $0x18, %r8
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add SRC, %r8
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shl $32, %r9
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mov (%r8), %r8d
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xor %r8, %r9
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.Lld_partial_4:
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movq %r9, MSG
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mov LEN, %r8
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and $0x8, %r8
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jz .Lld_partial_8
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mov LEN, %r8
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and $0x10, %r8
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add SRC, %r8
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pslldq $8, MSG
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movq (%r8), T0
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pxor T0, MSG
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.Lld_partial_8:
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ret
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ENDPROC(__load_partial)
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/*
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* __store_partial: internal ABI
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* input:
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* LEN - bytes
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* DST - dst
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* output:
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* T0 - message block
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* changed:
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* %r8
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* %r9
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* %r10
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*/
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__store_partial:
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mov LEN, %r8
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mov DST, %r9
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movq T0, %r10
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cmp $8, %r8
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jl .Lst_partial_8
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mov %r10, (%r9)
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psrldq $8, T0
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movq T0, %r10
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sub $8, %r8
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add $8, %r9
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.Lst_partial_8:
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cmp $4, %r8
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jl .Lst_partial_4
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mov %r10d, (%r9)
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shr $32, %r10
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sub $4, %r8
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add $4, %r9
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.Lst_partial_4:
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cmp $2, %r8
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jl .Lst_partial_2
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mov %r10w, (%r9)
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shr $0x10, %r10
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sub $2, %r8
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add $2, %r9
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.Lst_partial_2:
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cmp $1, %r8
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jl .Lst_partial_1
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mov %r10b, (%r9)
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.Lst_partial_1:
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ret
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ENDPROC(__store_partial)
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.macro update
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movdqa STATE5, T0
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aesenc STATE0, STATE5
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aesenc STATE1, STATE0
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aesenc STATE2, STATE1
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aesenc STATE3, STATE2
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aesenc STATE4, STATE3
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aesenc T0, STATE4
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.endm
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.macro update0 m
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update
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pxor \m, STATE5
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.endm
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.macro update1 m
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update
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pxor \m, STATE4
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.endm
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.macro update2 m
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update
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pxor \m, STATE3
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.endm
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.macro update3 m
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update
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pxor \m, STATE2
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.endm
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.macro update4 m
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update
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pxor \m, STATE1
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.endm
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.macro update5 m
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update
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pxor \m, STATE0
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.endm
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.macro state_load
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movdqu 0x00(STATEP), STATE0
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movdqu 0x10(STATEP), STATE1
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movdqu 0x20(STATEP), STATE2
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movdqu 0x30(STATEP), STATE3
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movdqu 0x40(STATEP), STATE4
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movdqu 0x50(STATEP), STATE5
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.endm
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.macro state_store s0 s1 s2 s3 s4 s5
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movdqu \s5, 0x00(STATEP)
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movdqu \s0, 0x10(STATEP)
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movdqu \s1, 0x20(STATEP)
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movdqu \s2, 0x30(STATEP)
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movdqu \s3, 0x40(STATEP)
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movdqu \s4, 0x50(STATEP)
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.endm
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.macro state_store0
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state_store STATE0 STATE1 STATE2 STATE3 STATE4 STATE5
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.endm
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.macro state_store1
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state_store STATE5 STATE0 STATE1 STATE2 STATE3 STATE4
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.endm
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.macro state_store2
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state_store STATE4 STATE5 STATE0 STATE1 STATE2 STATE3
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.endm
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.macro state_store3
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state_store STATE3 STATE4 STATE5 STATE0 STATE1 STATE2
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.endm
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.macro state_store4
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state_store STATE2 STATE3 STATE4 STATE5 STATE0 STATE1
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.endm
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.macro state_store5
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state_store STATE1 STATE2 STATE3 STATE4 STATE5 STATE0
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.endm
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/*
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* void crypto_aegis256_aesni_init(void *state, const void *key, const void *iv);
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*/
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ENTRY(crypto_aegis256_aesni_init)
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FRAME_BEGIN
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/* load key: */
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movdqa 0x00(%rsi), MSG
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movdqa 0x10(%rsi), T1
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movdqa MSG, STATE4
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movdqa T1, STATE5
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/* load IV: */
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movdqu 0x00(%rdx), T2
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movdqu 0x10(%rdx), T3
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pxor MSG, T2
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pxor T1, T3
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movdqa T2, STATE0
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movdqa T3, STATE1
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/* load the constants: */
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movdqa .Laegis256_const_0, STATE3
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movdqa .Laegis256_const_1, STATE2
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pxor STATE3, STATE4
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pxor STATE2, STATE5
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/* update 10 times with IV and KEY: */
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update0 MSG
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update1 T1
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update2 T2
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update3 T3
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update4 MSG
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update5 T1
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update0 T2
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update1 T3
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update2 MSG
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update3 T1
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update4 T2
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update5 T3
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update0 MSG
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update1 T1
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update2 T2
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update3 T3
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state_store3
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FRAME_END
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ret
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ENDPROC(crypto_aegis256_aesni_init)
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.macro ad_block a i
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movdq\a (\i * 0x10)(SRC), MSG
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update\i MSG
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sub $0x10, LEN
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cmp $0x10, LEN
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jl .Lad_out_\i
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.endm
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/*
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* void crypto_aegis256_aesni_ad(void *state, unsigned int length,
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* const void *data);
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*/
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ENTRY(crypto_aegis256_aesni_ad)
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FRAME_BEGIN
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cmp $0x10, LEN
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jb .Lad_out
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state_load
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mov SRC, %r8
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and $0xf, %r8
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jnz .Lad_u_loop
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.align 8
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.Lad_a_loop:
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ad_block a 0
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ad_block a 1
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ad_block a 2
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ad_block a 3
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ad_block a 4
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ad_block a 5
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add $0x60, SRC
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jmp .Lad_a_loop
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.align 8
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.Lad_u_loop:
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ad_block u 0
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ad_block u 1
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ad_block u 2
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ad_block u 3
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ad_block u 4
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ad_block u 5
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add $0x60, SRC
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jmp .Lad_u_loop
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.Lad_out_0:
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state_store0
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FRAME_END
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ret
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.Lad_out_1:
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state_store1
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FRAME_END
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ret
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.Lad_out_2:
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state_store2
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FRAME_END
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ret
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.Lad_out_3:
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state_store3
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FRAME_END
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ret
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.Lad_out_4:
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state_store4
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FRAME_END
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ret
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.Lad_out_5:
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state_store5
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FRAME_END
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ret
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.Lad_out:
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FRAME_END
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ret
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ENDPROC(crypto_aegis256_aesni_ad)
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.macro crypt m s0 s1 s2 s3 s4 s5
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pxor \s1, \m
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pxor \s4, \m
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pxor \s5, \m
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movdqa \s2, T3
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pand \s3, T3
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pxor T3, \m
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.endm
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.macro crypt0 m
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crypt \m STATE0 STATE1 STATE2 STATE3 STATE4 STATE5
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.endm
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.macro crypt1 m
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crypt \m STATE5 STATE0 STATE1 STATE2 STATE3 STATE4
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.endm
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.macro crypt2 m
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crypt \m STATE4 STATE5 STATE0 STATE1 STATE2 STATE3
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.endm
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.macro crypt3 m
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crypt \m STATE3 STATE4 STATE5 STATE0 STATE1 STATE2
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.endm
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.macro crypt4 m
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crypt \m STATE2 STATE3 STATE4 STATE5 STATE0 STATE1
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.endm
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.macro crypt5 m
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crypt \m STATE1 STATE2 STATE3 STATE4 STATE5 STATE0
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.endm
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.macro encrypt_block a i
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movdq\a (\i * 0x10)(SRC), MSG
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movdqa MSG, T0
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crypt\i T0
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movdq\a T0, (\i * 0x10)(DST)
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update\i MSG
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sub $0x10, LEN
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cmp $0x10, LEN
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jl .Lenc_out_\i
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.endm
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.macro decrypt_block a i
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movdq\a (\i * 0x10)(SRC), MSG
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crypt\i MSG
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movdq\a MSG, (\i * 0x10)(DST)
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update\i MSG
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sub $0x10, LEN
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cmp $0x10, LEN
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jl .Ldec_out_\i
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.endm
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/*
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* void crypto_aegis256_aesni_enc(void *state, unsigned int length,
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* const void *src, void *dst);
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*/
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ENTRY(crypto_aegis256_aesni_enc)
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FRAME_BEGIN
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cmp $0x10, LEN
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jb .Lenc_out
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state_load
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mov SRC, %r8
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or DST, %r8
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and $0xf, %r8
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jnz .Lenc_u_loop
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.align 8
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.Lenc_a_loop:
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encrypt_block a 0
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encrypt_block a 1
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encrypt_block a 2
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encrypt_block a 3
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encrypt_block a 4
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encrypt_block a 5
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add $0x60, SRC
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add $0x60, DST
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jmp .Lenc_a_loop
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.align 8
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.Lenc_u_loop:
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encrypt_block u 0
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encrypt_block u 1
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encrypt_block u 2
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encrypt_block u 3
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encrypt_block u 4
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encrypt_block u 5
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add $0x60, SRC
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add $0x60, DST
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jmp .Lenc_u_loop
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.Lenc_out_0:
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state_store0
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FRAME_END
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ret
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.Lenc_out_1:
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state_store1
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FRAME_END
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ret
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.Lenc_out_2:
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state_store2
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FRAME_END
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ret
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.Lenc_out_3:
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state_store3
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FRAME_END
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ret
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.Lenc_out_4:
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state_store4
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FRAME_END
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ret
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.Lenc_out_5:
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state_store5
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FRAME_END
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ret
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.Lenc_out:
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FRAME_END
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ret
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ENDPROC(crypto_aegis256_aesni_enc)
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/*
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* void crypto_aegis256_aesni_enc_tail(void *state, unsigned int length,
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* const void *src, void *dst);
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*/
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ENTRY(crypto_aegis256_aesni_enc_tail)
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FRAME_BEGIN
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state_load
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/* encrypt message: */
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call __load_partial
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movdqa MSG, T0
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crypt0 T0
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call __store_partial
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update0 MSG
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state_store0
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FRAME_END
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ret
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ENDPROC(crypto_aegis256_aesni_enc_tail)
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/*
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* void crypto_aegis256_aesni_dec(void *state, unsigned int length,
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* const void *src, void *dst);
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*/
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ENTRY(crypto_aegis256_aesni_dec)
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FRAME_BEGIN
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cmp $0x10, LEN
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jb .Ldec_out
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state_load
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mov SRC, %r8
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or DST, %r8
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and $0xF, %r8
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jnz .Ldec_u_loop
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.align 8
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.Ldec_a_loop:
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decrypt_block a 0
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decrypt_block a 1
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decrypt_block a 2
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decrypt_block a 3
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decrypt_block a 4
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decrypt_block a 5
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add $0x60, SRC
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add $0x60, DST
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jmp .Ldec_a_loop
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.align 8
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.Ldec_u_loop:
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decrypt_block u 0
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decrypt_block u 1
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decrypt_block u 2
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decrypt_block u 3
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decrypt_block u 4
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decrypt_block u 5
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add $0x60, SRC
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add $0x60, DST
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jmp .Ldec_u_loop
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.Ldec_out_0:
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|
state_store0
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out_1:
|
|
state_store1
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out_2:
|
|
state_store2
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out_3:
|
|
state_store3
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out_4:
|
|
state_store4
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out_5:
|
|
state_store5
|
|
FRAME_END
|
|
ret
|
|
|
|
.Ldec_out:
|
|
FRAME_END
|
|
ret
|
|
ENDPROC(crypto_aegis256_aesni_dec)
|
|
|
|
/*
|
|
* void crypto_aegis256_aesni_dec_tail(void *state, unsigned int length,
|
|
* const void *src, void *dst);
|
|
*/
|
|
ENTRY(crypto_aegis256_aesni_dec_tail)
|
|
FRAME_BEGIN
|
|
|
|
state_load
|
|
|
|
/* decrypt message: */
|
|
call __load_partial
|
|
|
|
crypt0 MSG
|
|
|
|
movdqa MSG, T0
|
|
call __store_partial
|
|
|
|
/* mask with byte count: */
|
|
movq LEN, T0
|
|
punpcklbw T0, T0
|
|
punpcklbw T0, T0
|
|
punpcklbw T0, T0
|
|
punpcklbw T0, T0
|
|
movdqa .Laegis256_counter, T1
|
|
pcmpgtb T1, T0
|
|
pand T0, MSG
|
|
|
|
update0 MSG
|
|
|
|
state_store0
|
|
|
|
FRAME_END
|
|
ret
|
|
ENDPROC(crypto_aegis256_aesni_dec_tail)
|
|
|
|
/*
|
|
* void crypto_aegis256_aesni_final(void *state, void *tag_xor,
|
|
* u64 assoclen, u64 cryptlen);
|
|
*/
|
|
ENTRY(crypto_aegis256_aesni_final)
|
|
FRAME_BEGIN
|
|
|
|
state_load
|
|
|
|
/* prepare length block: */
|
|
movq %rdx, MSG
|
|
movq %rcx, T0
|
|
pslldq $8, T0
|
|
pxor T0, MSG
|
|
psllq $3, MSG /* multiply by 8 (to get bit count) */
|
|
|
|
pxor STATE3, MSG
|
|
|
|
/* update state: */
|
|
update0 MSG
|
|
update1 MSG
|
|
update2 MSG
|
|
update3 MSG
|
|
update4 MSG
|
|
update5 MSG
|
|
update0 MSG
|
|
|
|
/* xor tag: */
|
|
movdqu (%rsi), MSG
|
|
|
|
pxor STATE0, MSG
|
|
pxor STATE1, MSG
|
|
pxor STATE2, MSG
|
|
pxor STATE3, MSG
|
|
pxor STATE4, MSG
|
|
pxor STATE5, MSG
|
|
|
|
movdqu MSG, (%rsi)
|
|
|
|
FRAME_END
|
|
ret
|
|
ENDPROC(crypto_aegis256_aesni_final)
|