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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa the gnu gpl is contained in usr doc copyright gpl on a debian system and in the file copying in the linux kernel source extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 6 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520170857.643862682@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
493 lines
16 KiB
C
493 lines
16 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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Madge Horizon ATM Adapter driver.
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Copyright (C) 1995-1999 Madge Networks Ltd.
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*/
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/*
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IMPORTANT NOTE: Madge Networks no longer makes the adapters
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supported by this driver and makes no commitment to maintain it.
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*/
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/* too many macros - change to inline functions */
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#ifndef DRIVER_ATM_HORIZON_H
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#define DRIVER_ATM_HORIZON_H
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#ifdef CONFIG_ATM_HORIZON_DEBUG
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#define DEBUG_HORIZON
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#endif
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#define DEV_LABEL "hrz"
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#ifndef PCI_VENDOR_ID_MADGE
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#define PCI_VENDOR_ID_MADGE 0x10B6
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#endif
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#ifndef PCI_DEVICE_ID_MADGE_HORIZON
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#define PCI_DEVICE_ID_MADGE_HORIZON 0x1000
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#endif
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// diagnostic output
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#define PRINTK(severity,format,args...) \
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printk(severity DEV_LABEL ": " format "\n" , ## args)
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#ifdef DEBUG_HORIZON
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#define DBG_ERR 0x0001
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#define DBG_WARN 0x0002
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#define DBG_INFO 0x0004
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#define DBG_VCC 0x0008
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#define DBG_QOS 0x0010
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#define DBG_TX 0x0020
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#define DBG_RX 0x0040
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#define DBG_SKB 0x0080
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#define DBG_IRQ 0x0100
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#define DBG_FLOW 0x0200
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#define DBG_BUS 0x0400
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#define DBG_REGS 0x0800
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#define DBG_DATA 0x1000
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#define DBG_MASK 0x1fff
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/* the ## prevents the annoying double expansion of the macro arguments */
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/* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
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#define PRINTDB(bits,format,args...) \
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( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
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#define PRINTDM(bits,format,args...) \
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( (debug & (bits)) ? printk (format , ## args) : 1 )
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#define PRINTDE(bits,format,args...) \
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( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
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#define PRINTD(bits,format,args...) \
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( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
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#else
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#define PRINTD(bits,format,args...)
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#define PRINTDB(bits,format,args...)
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#define PRINTDM(bits,format,args...)
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#define PRINTDE(bits,format,args...)
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#endif
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#define PRINTDD(sec,fmt,args...)
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#define PRINTDDB(sec,fmt,args...)
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#define PRINTDDM(sec,fmt,args...)
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#define PRINTDDE(sec,fmt,args...)
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// fixed constants
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#define SPARE_BUFFER_POOL_SIZE MAX_VCS
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#define HRZ_MAX_VPI 4
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#define MIN_PCI_LATENCY 48 // 24 IS TOO SMALL
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/* Horizon specific bits */
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/* Register offsets */
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#define HRZ_IO_EXTENT 0x80
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#define DATA_PORT_OFF 0x00
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#define TX_CHANNEL_PORT_OFF 0x04
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#define TX_DESCRIPTOR_PORT_OFF 0x08
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#define MEMORY_PORT_OFF 0x0C
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#define MEM_WR_ADDR_REG_OFF 0x14
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#define MEM_RD_ADDR_REG_OFF 0x18
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#define CONTROL_0_REG 0x1C
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#define INT_SOURCE_REG_OFF 0x20
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#define INT_ENABLE_REG_OFF 0x24
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#define MASTER_RX_ADDR_REG_OFF 0x28
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#define MASTER_RX_COUNT_REG_OFF 0x2C
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#define MASTER_TX_ADDR_REG_OFF 0x30
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#define MASTER_TX_COUNT_REG_OFF 0x34
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#define TX_DESCRIPTOR_REG_OFF 0x38
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#define TX_CHANNEL_CONFIG_COMMAND_OFF 0x40
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#define TX_CHANNEL_CONFIG_DATA_OFF 0x44
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#define TX_FREE_BUFFER_COUNT_OFF 0x48
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#define RX_FREE_BUFFER_COUNT_OFF 0x4C
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#define TX_CONFIG_OFF 0x50
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#define TX_STATUS_OFF 0x54
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#define RX_CONFIG_OFF 0x58
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#define RX_LINE_CONFIG_OFF 0x5C
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#define RX_QUEUE_RD_PTR_OFF 0x60
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#define RX_QUEUE_WR_PTR_OFF 0x64
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#define MAX_AAL5_CELL_COUNT_OFF 0x68
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#define RX_CHANNEL_PORT_OFF 0x6C
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#define TX_CELL_COUNT_OFF 0x70
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#define RX_CELL_COUNT_OFF 0x74
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#define HEC_ERROR_COUNT_OFF 0x78
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#define UNASSIGNED_CELL_COUNT_OFF 0x7C
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/* Register bit definitions */
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/* Control 0 register */
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#define SEEPROM_DO 0x00000001
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#define SEEPROM_DI 0x00000002
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#define SEEPROM_SK 0x00000004
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#define SEEPROM_CS 0x00000008
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#define DEBUG_BIT_0 0x00000010
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#define DEBUG_BIT_1 0x00000020
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#define DEBUG_BIT_2 0x00000040
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// RESERVED 0x00000080
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#define DEBUG_BIT_0_OE 0x00000100
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#define DEBUG_BIT_1_OE 0x00000200
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#define DEBUG_BIT_2_OE 0x00000400
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// RESERVED 0x00000800
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#define DEBUG_BIT_0_STATE 0x00001000
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#define DEBUG_BIT_1_STATE 0x00002000
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#define DEBUG_BIT_2_STATE 0x00004000
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// RESERVED 0x00008000
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#define GENERAL_BIT_0 0x00010000
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#define GENERAL_BIT_1 0x00020000
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#define GENERAL_BIT_2 0x00040000
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#define GENERAL_BIT_3 0x00080000
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#define RESET_HORIZON 0x00100000
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#define RESET_ATM 0x00200000
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#define RESET_RX 0x00400000
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#define RESET_TX 0x00800000
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#define RESET_HOST 0x01000000
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// RESERVED 0x02000000
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#define TARGET_RETRY_DISABLE 0x04000000
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#define ATM_LAYER_SELECT 0x08000000
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#define ATM_LAYER_STATUS 0x10000000
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// RESERVED 0xE0000000
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/* Interrupt source and enable registers */
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#define RX_DATA_AV 0x00000001
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#define RX_DISABLED 0x00000002
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#define TIMING_MARKER 0x00000004
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#define FORCED 0x00000008
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#define RX_BUS_MASTER_COMPLETE 0x00000010
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#define TX_BUS_MASTER_COMPLETE 0x00000020
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#define ABR_TX_CELL_COUNT_INT 0x00000040
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#define DEBUG_INT 0x00000080
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// RESERVED 0xFFFFFF00
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/* PIO and Bus Mastering */
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#define MAX_PIO_COUNT 0x000000ff // 255 - make tunable?
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// 8188 is a hard limit for bus mastering
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#define MAX_TRANSFER_COUNT 0x00001ffc // 8188
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#define MASTER_TX_AUTO_APPEND_DESC 0x80000000
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/* TX channel config command port */
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#define PCR_TIMER_ACCESS 0x0000
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#define SCR_TIMER_ACCESS 0x0001
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#define BUCKET_CAPACITY_ACCESS 0x0002
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#define BUCKET_FULLNESS_ACCESS 0x0003
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#define RATE_TYPE_ACCESS 0x0004
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// UNUSED 0x00F8
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#define TX_CHANNEL_CONFIG_MULT 0x0100
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// UNUSED 0xF800
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#define BUCKET_MAX_SIZE 0x003f
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/* TX channel config data port */
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#define CLOCK_SELECT_SHIFT 4
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#define CLOCK_DISABLE 0x00ff
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#define IDLE_RATE_TYPE 0x0
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#define ABR_RATE_TYPE 0x1
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#define VBR_RATE_TYPE 0x2
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#define CBR_RATE_TYPE 0x3
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/* TX config register */
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#define DRVR_DRVRBAR_ENABLE 0x0001
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#define TXCLK_MUX_SELECT_RCLK 0x0002
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#define TRANSMIT_TIMING_MARKER 0x0004
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#define LOOPBACK_TIMING_MARKER 0x0008
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#define TX_TEST_MODE_16MHz 0x0000
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#define TX_TEST_MODE_8MHz 0x0010
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#define TX_TEST_MODE_5_33MHz 0x0020
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#define TX_TEST_MODE_4MHz 0x0030
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#define TX_TEST_MODE_3_2MHz 0x0040
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#define TX_TEST_MODE_2_66MHz 0x0050
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#define TX_TEST_MODE_2_29MHz 0x0060
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#define TX_NORMAL_OPERATION 0x0070
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#define ABR_ROUND_ROBIN 0x0080
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/* TX status register */
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#define IDLE_CHANNELS_MASK 0x00FF
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#define ABR_CELL_COUNT_REACHED_MULT 0x0100
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#define ABR_CELL_COUNT_REACHED_MASK 0xFF
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/* RX config register */
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#define NON_USER_CELLS_IN_ONE_CHANNEL 0x0008
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#define RX_ENABLE 0x0010
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#define IGNORE_UNUSED_VPI_VCI_BITS_SET 0x0000
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#define NON_USER_UNUSED_VPI_VCI_BITS_SET 0x0020
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#define DISCARD_UNUSED_VPI_VCI_BITS_SET 0x0040
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/* RX line config register */
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#define SIGNAL_LOSS 0x0001
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#define FREQUENCY_DETECT_ERROR 0x0002
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#define LOCK_DETECT_ERROR 0x0004
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#define SELECT_INTERNAL_LOOPBACK 0x0008
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#define LOCK_DETECT_ENABLE 0x0010
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#define FREQUENCY_DETECT_ENABLE 0x0020
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#define USER_FRAQ 0x0040
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#define GXTALOUT_SELECT_DIV4 0x0080
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#define GXTALOUT_SELECT_NO_GATING 0x0100
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#define TIMING_MARKER_RECEIVED 0x0200
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/* RX channel port */
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#define RX_CHANNEL_MASK 0x03FF
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// UNUSED 0x3C00
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#define FLUSH_CHANNEL 0x4000
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#define RX_CHANNEL_UPDATE_IN_PROGRESS 0x8000
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/* Receive queue entry */
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#define RX_Q_ENTRY_LENGTH_MASK 0x0000FFFF
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#define RX_Q_ENTRY_CHANNEL_SHIFT 16
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#define SIMONS_DODGEY_MARKER 0x08000000
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#define RX_CONGESTION_EXPERIENCED 0x10000000
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#define RX_CRC_10_OK 0x20000000
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#define RX_CRC_32_OK 0x40000000
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#define RX_COMPLETE_FRAME 0x80000000
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/* Offsets and constants for use with the buffer memory */
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/* Buffer pointers and channel types */
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#define BUFFER_PTR_MASK 0x0000FFFF
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#define RX_INT_THRESHOLD_MULT 0x00010000
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#define RX_INT_THRESHOLD_MASK 0x07FF
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#define INT_EVERY_N_CELLS 0x08000000
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#define CONGESTION_EXPERIENCED 0x10000000
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#define FIRST_CELL_OF_AAL5_FRAME 0x20000000
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#define CHANNEL_TYPE_AAL5 0x00000000
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#define CHANNEL_TYPE_RAW_CELLS 0x40000000
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#define CHANNEL_TYPE_AAL3_4 0x80000000
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/* Buffer status stuff */
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#define BUFF_STATUS_MASK 0x00030000
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#define BUFF_STATUS_EMPTY 0x00000000
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#define BUFF_STATUS_CELL_AV 0x00010000
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#define BUFF_STATUS_LAST_CELL_AV 0x00020000
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/* Transmit channel stuff */
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/* Receive channel stuff */
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#define RX_CHANNEL_DISABLED 0x00000000
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#define RX_CHANNEL_IDLE 0x00000001
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/* General things */
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#define INITIAL_CRC 0xFFFFFFFF
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// A Horizon u32, a byte! Really nasty. Horizon pointers are (32 bit)
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// word addresses and so standard C pointer operations break (as they
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// assume byte addresses); so we pretend that Horizon words (and word
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// pointers) are bytes (and byte pointers) for the purposes of having
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// a memory map that works.
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typedef u8 HDW;
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typedef struct cell_buf {
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HDW payload[12];
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HDW next;
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HDW cell_count; // AAL5 rx bufs
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HDW res;
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union {
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HDW partial_crc; // AAL5 rx bufs
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HDW cell_header; // RAW bufs
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} u;
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} cell_buf;
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typedef struct tx_ch_desc {
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HDW rd_buf_type;
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HDW wr_buf_type;
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HDW partial_crc;
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HDW cell_header;
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} tx_ch_desc;
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typedef struct rx_ch_desc {
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HDW wr_buf_type;
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HDW rd_buf_type;
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} rx_ch_desc;
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typedef struct rx_q_entry {
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HDW entry;
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} rx_q_entry;
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#define TX_CHANS 8
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#define RX_CHANS 1024
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#define RX_QS 1024
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#define MAX_VCS RX_CHANS
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/* Horizon buffer memory map */
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// TX Channel Descriptors 2
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// TX Initial Buffers 8 // TX_CHANS
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#define BUFN1_SIZE 118 // (126 - TX_CHANS)
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// RX/TX Start/End Buffers 4
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#define BUFN2_SIZE 124
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// RX Queue Entries 64
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#define BUFN3_SIZE 192
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// RX Channel Descriptors 128
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#define BUFN4_SIZE 1408
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// TOTAL cell_buff chunks 2048
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// cell_buf bufs[2048];
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// HDW dws[32768];
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typedef struct MEMMAP {
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tx_ch_desc tx_descs[TX_CHANS]; // 8 * 4 = 32 , 0x0020
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cell_buf inittxbufs[TX_CHANS]; // these are really
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cell_buf bufn1[BUFN1_SIZE]; // part of this pool
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cell_buf txfreebufstart;
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cell_buf txfreebufend;
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cell_buf rxfreebufstart;
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cell_buf rxfreebufend; // 8+118+1+1+1+1+124 = 254
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cell_buf bufn2[BUFN2_SIZE]; // 16 * 254 = 4064 , 0x1000
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rx_q_entry rx_q_entries[RX_QS]; // 1 * 1024 = 1024 , 0x1400
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cell_buf bufn3[BUFN3_SIZE]; // 16 * 192 = 3072 , 0x2000
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rx_ch_desc rx_descs[MAX_VCS]; // 2 * 1024 = 2048 , 0x2800
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cell_buf bufn4[BUFN4_SIZE]; // 16 * 1408 = 22528 , 0x8000
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} MEMMAP;
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#define memmap ((MEMMAP *)0)
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/* end horizon specific bits */
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typedef enum {
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aal0,
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aal34,
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aal5
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} hrz_aal;
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typedef enum {
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tx_busy,
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rx_busy,
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ultra
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} hrz_flags;
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// a single struct pointed to by atm_vcc->dev_data
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typedef struct {
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unsigned int tx_rate;
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unsigned int rx_rate;
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u16 channel;
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u16 tx_xbr_bits;
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u16 tx_pcr_bits;
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#if 0
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u16 tx_scr_bits;
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u16 tx_bucket_bits;
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#endif
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hrz_aal aal;
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} hrz_vcc;
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struct hrz_dev {
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u32 iobase;
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u32 * membase;
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struct sk_buff * rx_skb; // skb being RXed
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unsigned int rx_bytes; // bytes remaining to RX within region
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void * rx_addr; // addr to send bytes to (for PIO)
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unsigned int rx_channel; // channel that the skb is going out on
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struct sk_buff * tx_skb; // skb being TXed
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unsigned int tx_bytes; // bytes remaining to TX within region
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void * tx_addr; // addr to send bytes from (for PIO)
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struct iovec * tx_iovec; // remaining regions
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unsigned int tx_regions; // number of remaining regions
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spinlock_t mem_lock;
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wait_queue_head_t tx_queue;
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u8 irq;
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unsigned long flags;
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u8 tx_last;
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u8 tx_idle;
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rx_q_entry * rx_q_reset;
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rx_q_entry * rx_q_entry;
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rx_q_entry * rx_q_wrap;
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struct atm_dev * atm_dev;
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u32 last_vc;
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int noof_spare_buffers;
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u16 spare_buffers[SPARE_BUFFER_POOL_SIZE];
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u16 tx_channel_record[TX_CHANS];
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// this is what we follow when we get incoming data
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u32 txer[MAX_VCS/32];
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struct atm_vcc * rxer[MAX_VCS];
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// cell rate allocation
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spinlock_t rate_lock;
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unsigned int rx_avail;
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unsigned int tx_avail;
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// dev stats
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unsigned long tx_cell_count;
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unsigned long rx_cell_count;
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unsigned long hec_error_count;
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unsigned long unassigned_cell_count;
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struct pci_dev * pci_dev;
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struct timer_list housekeeping;
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};
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typedef struct hrz_dev hrz_dev;
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/* macros for use later */
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#define BUF_PTR(cbptr) ((cbptr) - (cell_buf *) 0)
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#define INTERESTING_INTERRUPTS \
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(RX_DATA_AV | RX_DISABLED | TX_BUS_MASTER_COMPLETE | RX_BUS_MASTER_COMPLETE)
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// 190 cells by default (192 TX buffers - 2 elbow room, see docs)
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#define TX_AAL5_LIMIT (190*ATM_CELL_PAYLOAD-ATM_AAL5_TRAILER) // 9112
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// Have enough RX buffers (unless we allow other buffer splits)
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#define RX_AAL5_LIMIT ATM_MAX_AAL5_PDU
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/* multi-statement macro protector */
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#define DW(x) do{ x } while(0)
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#define HRZ_DEV(atm_dev) ((hrz_dev *) (atm_dev)->dev_data)
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#define HRZ_VCC(atm_vcc) ((hrz_vcc *) (atm_vcc)->dev_data)
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/* Turn the LEDs on and off */
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// The LEDs bits are upside down in that setting the bit in the debug
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// register will turn the appropriate LED off.
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#define YELLOW_LED DEBUG_BIT_0
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#define GREEN_LED DEBUG_BIT_1
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#define YELLOW_LED_OE DEBUG_BIT_0_OE
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#define GREEN_LED_OE DEBUG_BIT_1_OE
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#define GREEN_LED_OFF(dev) \
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wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
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#define GREEN_LED_ON(dev) \
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wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
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#define YELLOW_LED_OFF(dev) \
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wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
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#define YELLOW_LED_ON(dev) \
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wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
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typedef enum {
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round_up,
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round_down,
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round_nearest
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} rounding;
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#endif /* DRIVER_ATM_HORIZON_H */
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