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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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fcced66f20
On the axg, frddr could only be connected to 1 downstream element, so the playback was possible on 1 interface only at a time. On the g12a, the frddr may connect and wait for the request of up to 3 downstream elements. With this, it possible for single playback to be played on several interfaces at the same time. Like the toddr fifo, the g12a frddr also need to take care of resetting the read pointer to the initial fifo address when preparing a playback. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Mark Brown <broonie@kernel.org>
279 lines
8.8 KiB
C
279 lines
8.8 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Copyright (c) 2018 BayLibre, SAS.
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// Author: Jerome Brunet <jbrunet@baylibre.com>
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/*
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* This driver implements the frontend playback DAI of AXG and G12A based SoCs
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*/
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "axg-fifo.h"
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#define CTRL0_FRDDR_PP_MODE BIT(30)
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#define CTRL0_SEL1_EN_SHIFT 3
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#define CTRL0_SEL2_SHIFT 4
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#define CTRL0_SEL2_EN_SHIFT 7
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#define CTRL0_SEL3_SHIFT 8
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#define CTRL0_SEL3_EN_SHIFT 11
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#define CTRL1_FRDDR_FORCE_FINISH BIT(12)
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static int g12a_frddr_dai_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
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/* Reset the read pointer to the FIFO_INIT_ADDR */
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_FRDDR_FORCE_FINISH, 0);
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_FRDDR_FORCE_FINISH, CTRL1_FRDDR_FORCE_FINISH);
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_FRDDR_FORCE_FINISH, 0);
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return 0;
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}
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static int axg_frddr_dai_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
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unsigned int fifo_depth, fifo_threshold;
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int ret;
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/* Enable pclk to access registers and clock the fifo ip */
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ret = clk_prepare_enable(fifo->pclk);
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if (ret)
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return ret;
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/* Apply single buffer mode to the interface */
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regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0);
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/*
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* TODO: We could adapt the fifo depth and the fifo threshold
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* depending on the expected memory throughput and lantencies
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* For now, we'll just use the same values as the vendor kernel
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* Depth and threshold are zero based.
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*/
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fifo_depth = AXG_FIFO_MIN_CNT - 1;
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fifo_threshold = (AXG_FIFO_MIN_CNT / 2) - 1;
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regmap_update_bits(fifo->map, FIFO_CTRL1,
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CTRL1_FRDDR_DEPTH_MASK | CTRL1_THRESHOLD_MASK,
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CTRL1_FRDDR_DEPTH(fifo_depth) |
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CTRL1_THRESHOLD(fifo_threshold));
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return 0;
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}
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static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai);
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clk_disable_unprepare(fifo->pclk);
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}
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static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd,
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struct snd_soc_dai *dai)
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{
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return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK);
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}
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static const struct snd_soc_dai_ops axg_frddr_ops = {
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.startup = axg_frddr_dai_startup,
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.shutdown = axg_frddr_dai_shutdown,
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};
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static struct snd_soc_dai_driver axg_frddr_dai_drv = {
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.name = "FRDDR",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = AXG_FIFO_CH_MAX,
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.rates = AXG_FIFO_RATES,
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.formats = AXG_FIFO_FORMATS,
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},
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.ops = &axg_frddr_ops,
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.pcm_new = axg_frddr_pcm_new,
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};
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static const char * const axg_frddr_sel_texts[] = {
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"OUT 0", "OUT 1", "OUT 2", "OUT 3"
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};
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static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
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axg_frddr_sel_texts);
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static const struct snd_kcontrol_new axg_frddr_out_demux =
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SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum);
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static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = {
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SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0,
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&axg_frddr_out_demux),
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SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
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};
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static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = {
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{ "SINK SEL", NULL, "Playback" },
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{ "OUT 0", "OUT 0", "SINK SEL" },
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{ "OUT 1", "OUT 1", "SINK SEL" },
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{ "OUT 2", "OUT 2", "SINK SEL" },
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{ "OUT 3", "OUT 3", "SINK SEL" },
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};
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static const struct snd_soc_component_driver axg_frddr_component_drv = {
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.dapm_widgets = axg_frddr_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets),
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.dapm_routes = axg_frddr_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes),
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.ops = &axg_fifo_pcm_ops
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};
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static const struct axg_fifo_match_data axg_frddr_match_data = {
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.component_drv = &axg_frddr_component_drv,
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.dai_drv = &axg_frddr_dai_drv
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};
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static const struct snd_soc_dai_ops g12a_frddr_ops = {
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.prepare = g12a_frddr_dai_prepare,
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.startup = axg_frddr_dai_startup,
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.shutdown = axg_frddr_dai_shutdown,
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};
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static struct snd_soc_dai_driver g12a_frddr_dai_drv = {
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.name = "FRDDR",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = AXG_FIFO_CH_MAX,
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.rates = AXG_FIFO_RATES,
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.formats = AXG_FIFO_FORMATS,
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},
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.ops = &g12a_frddr_ops,
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.pcm_new = axg_frddr_pcm_new,
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};
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static const char * const g12a_frddr_sel_texts[] = {
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"OUT 0", "OUT 1", "OUT 2", "OUT 3", "OUT 4",
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};
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static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel1_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT,
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g12a_frddr_sel_texts);
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static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel2_enum, FIFO_CTRL0, CTRL0_SEL2_SHIFT,
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g12a_frddr_sel_texts);
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static SOC_ENUM_SINGLE_DECL(g12a_frddr_sel3_enum, FIFO_CTRL0, CTRL0_SEL3_SHIFT,
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g12a_frddr_sel_texts);
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static const struct snd_kcontrol_new g12a_frddr_out1_demux =
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SOC_DAPM_ENUM("Output Src 1", g12a_frddr_sel1_enum);
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static const struct snd_kcontrol_new g12a_frddr_out2_demux =
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SOC_DAPM_ENUM("Output Src 2", g12a_frddr_sel2_enum);
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static const struct snd_kcontrol_new g12a_frddr_out3_demux =
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SOC_DAPM_ENUM("Output Src 3", g12a_frddr_sel3_enum);
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static const struct snd_kcontrol_new g12a_frddr_out1_enable =
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SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
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CTRL0_SEL1_EN_SHIFT, 1, 0);
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static const struct snd_kcontrol_new g12a_frddr_out2_enable =
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SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
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CTRL0_SEL2_EN_SHIFT, 1, 0);
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static const struct snd_kcontrol_new g12a_frddr_out3_enable =
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SOC_DAPM_SINGLE_AUTODISABLE("Switch", FIFO_CTRL0,
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CTRL0_SEL3_EN_SHIFT, 1, 0);
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static const struct snd_soc_dapm_widget g12a_frddr_dapm_widgets[] = {
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SND_SOC_DAPM_AIF_OUT("SRC 1", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("SRC 2", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("SRC 3", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_SWITCH("SRC 1 EN", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out1_enable),
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SND_SOC_DAPM_SWITCH("SRC 2 EN", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out2_enable),
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SND_SOC_DAPM_SWITCH("SRC 3 EN", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out3_enable),
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SND_SOC_DAPM_DEMUX("SINK 1 SEL", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out1_demux),
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SND_SOC_DAPM_DEMUX("SINK 2 SEL", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out2_demux),
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SND_SOC_DAPM_DEMUX("SINK 3 SEL", SND_SOC_NOPM, 0, 0,
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&g12a_frddr_out3_demux),
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SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0),
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SND_SOC_DAPM_AIF_OUT("OUT 4", NULL, 0, SND_SOC_NOPM, 0, 0),
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};
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static const struct snd_soc_dapm_route g12a_frddr_dapm_routes[] = {
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{ "SRC 1", NULL, "Playback" },
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{ "SRC 2", NULL, "Playback" },
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{ "SRC 3", NULL, "Playback" },
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{ "SRC 1 EN", "Switch", "SRC 1" },
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{ "SRC 2 EN", "Switch", "SRC 2" },
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{ "SRC 3 EN", "Switch", "SRC 3" },
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{ "SINK 1 SEL", NULL, "SRC 1 EN" },
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{ "SINK 2 SEL", NULL, "SRC 2 EN" },
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{ "SINK 3 SEL", NULL, "SRC 3 EN" },
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{ "OUT 0", "OUT 0", "SINK 1 SEL" },
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{ "OUT 1", "OUT 1", "SINK 1 SEL" },
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{ "OUT 2", "OUT 2", "SINK 1 SEL" },
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{ "OUT 3", "OUT 3", "SINK 1 SEL" },
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{ "OUT 4", "OUT 4", "SINK 1 SEL" },
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{ "OUT 0", "OUT 0", "SINK 2 SEL" },
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{ "OUT 1", "OUT 1", "SINK 2 SEL" },
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{ "OUT 2", "OUT 2", "SINK 2 SEL" },
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{ "OUT 3", "OUT 3", "SINK 2 SEL" },
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{ "OUT 4", "OUT 4", "SINK 2 SEL" },
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{ "OUT 0", "OUT 0", "SINK 3 SEL" },
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{ "OUT 1", "OUT 1", "SINK 3 SEL" },
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{ "OUT 2", "OUT 2", "SINK 3 SEL" },
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{ "OUT 3", "OUT 3", "SINK 3 SEL" },
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{ "OUT 4", "OUT 4", "SINK 3 SEL" },
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};
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static const struct snd_soc_component_driver g12a_frddr_component_drv = {
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.dapm_widgets = g12a_frddr_dapm_widgets,
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.num_dapm_widgets = ARRAY_SIZE(g12a_frddr_dapm_widgets),
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.dapm_routes = g12a_frddr_dapm_routes,
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.num_dapm_routes = ARRAY_SIZE(g12a_frddr_dapm_routes),
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.ops = &g12a_fifo_pcm_ops
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};
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static const struct axg_fifo_match_data g12a_frddr_match_data = {
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.component_drv = &g12a_frddr_component_drv,
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.dai_drv = &g12a_frddr_dai_drv
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};
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static const struct of_device_id axg_frddr_of_match[] = {
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{
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.compatible = "amlogic,axg-frddr",
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.data = &axg_frddr_match_data,
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}, {
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.compatible = "amlogic,g12a-frddr",
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.data = &g12a_frddr_match_data,
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}, {}
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};
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MODULE_DEVICE_TABLE(of, axg_frddr_of_match);
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static struct platform_driver axg_frddr_pdrv = {
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.probe = axg_fifo_probe,
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.driver = {
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.name = "axg-frddr",
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.of_match_table = axg_frddr_of_match,
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},
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};
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module_platform_driver(axg_frddr_pdrv);
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MODULE_DESCRIPTION("Amlogic AXG/G12A playback fifo driver");
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MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
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MODULE_LICENSE("GPL v2");
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