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5b92415e64
Similar to commitac0e331a62
("drm/i915: Tighten atomicity of i915_active_acquire vs i915_active_release") we have the same race of trying to pin the context underneath a mutex while allowing the decrement to be atomic outside of that mutex. This leads to the problem where two threads may simultaneously try to pin the context and the second not notice that they needed to repin the context. <2> [198.669621] kernel BUG at drivers/gpu/drm/i915/gt/intel_timeline.c:387! <4> [198.669703] invalid opcode: 0000 [#1] PREEMPT SMP PTI <4> [198.669712] CPU: 0 PID: 1246 Comm: gem_exec_create Tainted: G U W 5.5.0-rc6-CI-CI_DRM_7755+ #1 <4> [198.669723] Hardware name: /NUC7i5BNB, BIOS BNKBL357.86A.0054.2017.1025.1822 10/25/2017 <4> [198.669776] RIP: 0010:timeline_advance+0x7b/0xe0 [i915] <4> [198.669785] Code: 00 48 c7 c2 10 f1 46 a0 48 c7 c7 70 1b 32 a0 e8 bb dd e7 e0 bf 01 00 00 00 e8 d1 af e7 e0 31 f6 bf 09 00 00 00 e8 35 ef d8 e0 <0f> 0b 48 c7 c1 48 fa 49 a0 ba 84 01 00 00 48 c7 c6 10 f1 46 a0 48 <4> [198.669803] RSP: 0018:ffffc900004c3a38 EFLAGS: 00010296 <4> [198.669810] RAX: ffff888270b35140 RBX: ffff88826f32ee00 RCX: 0000000000000006 <4> [198.669818] RDX: 00000000000017c5 RSI: 0000000000000000 RDI: 0000000000000009 <4> [198.669826] RBP: ffffc900004c3a64 R08: 0000000000000000 R09: 0000000000000000 <4> [198.669834] R10: 0000000000000000 R11: 0000000000000000 R12: ffff88826f9b5980 <4> [198.669841] R13: 0000000000000cc0 R14: ffffc900004c3dc0 R15: ffff888253610068 <4> [198.669849] FS: 00007f63e663fe40(0000) GS:ffff888276c00000(0000) knlGS:0000000000000000 <4> [198.669857] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [198.669864] CR2: 00007f171f8e39a8 CR3: 000000026b1f6005 CR4: 00000000003606f0 <4> [198.669872] Call Trace: <4> [198.669924] intel_timeline_get_seqno+0x12/0x40 [i915] <4> [198.669977] __i915_request_create+0x76/0x5a0 [i915] <4> [198.670024] i915_request_create+0x86/0x1c0 [i915] <4> [198.670068] i915_gem_do_execbuffer+0xbf2/0x2500 [i915] <4> [198.670082] ? __lock_acquire+0x460/0x15d0 <4> [198.670128] i915_gem_execbuffer2_ioctl+0x11f/0x470 [i915] <4> [198.670171] ? i915_gem_execbuffer_ioctl+0x300/0x300 [i915] <4> [198.670181] drm_ioctl_kernel+0xa7/0xf0 <4> [198.670188] drm_ioctl+0x2e1/0x390 <4> [198.670233] ? i915_gem_execbuffer_ioctl+0x300/0x300 [i915] Fixes:8413502238
("drm/i915/gt: Drop mutex serialisation between context pin/unpin") References:ac0e331a62
("drm/i915: Tighten atomicity of i915_active_acquire vs i915_active_release") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200127152829.2842149-1-chris@chris-wilson.co.uk (cherry picked from commite5429340bf
) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
219 lines
7.7 KiB
C
219 lines
7.7 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef _I915_ACTIVE_H_
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#define _I915_ACTIVE_H_
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#include <linux/lockdep.h>
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#include "i915_active_types.h"
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#include "i915_request.h"
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struct i915_request;
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struct intel_engine_cs;
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struct intel_timeline;
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/*
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* We treat requests as fences. This is not be to confused with our
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* "fence registers" but pipeline synchronisation objects ala GL_ARB_sync.
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* We use the fences to synchronize access from the CPU with activity on the
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* GPU, for example, we should not rewrite an object's PTE whilst the GPU
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* is reading them. We also track fences at a higher level to provide
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* implicit synchronisation around GEM objects, e.g. set-domain will wait
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* for outstanding GPU rendering before marking the object ready for CPU
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* access, or a pageflip will wait until the GPU is complete before showing
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* the frame on the scanout.
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*
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* In order to use a fence, the object must track the fence it needs to
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* serialise with. For example, GEM objects want to track both read and
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* write access so that we can perform concurrent read operations between
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* the CPU and GPU engines, as well as waiting for all rendering to
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* complete, or waiting for the last GPU user of a "fence register". The
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* object then embeds a #i915_active_fence to track the most recent (in
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* retirement order) request relevant for the desired mode of access.
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* The #i915_active_fence is updated with i915_active_fence_set() to
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* track the most recent fence request, typically this is done as part of
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* i915_vma_move_to_active().
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*
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* When the #i915_active_fence completes (is retired), it will
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* signal its completion to the owner through a callback as well as mark
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* itself as idle (i915_active_fence.request == NULL). The owner
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* can then perform any action, such as delayed freeing of an active
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* resource including itself.
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*/
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void i915_active_noop(struct dma_fence *fence, struct dma_fence_cb *cb);
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/**
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* __i915_active_fence_init - prepares the activity tracker for use
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* @active - the active tracker
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* @fence - initial fence to track, can be NULL
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* @func - a callback when then the tracker is retired (becomes idle),
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* can be NULL
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*
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* i915_active_fence_init() prepares the embedded @active struct for use as
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* an activity tracker, that is for tracking the last known active fence
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* associated with it. When the last fence becomes idle, when it is retired
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* after completion, the optional callback @func is invoked.
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*/
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static inline void
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__i915_active_fence_init(struct i915_active_fence *active,
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void *fence,
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dma_fence_func_t fn)
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{
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RCU_INIT_POINTER(active->fence, fence);
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active->cb.func = fn ?: i915_active_noop;
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}
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#define INIT_ACTIVE_FENCE(A) \
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__i915_active_fence_init((A), NULL, NULL)
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struct dma_fence *
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__i915_active_fence_set(struct i915_active_fence *active,
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struct dma_fence *fence);
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/**
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* i915_active_fence_set - updates the tracker to watch the current fence
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* @active - the active tracker
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* @rq - the request to watch
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*
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* i915_active_fence_set() watches the given @rq for completion. While
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* that @rq is busy, the @active reports busy. When that @rq is signaled
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* (or else retired) the @active tracker is updated to report idle.
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*/
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int __must_check
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i915_active_fence_set(struct i915_active_fence *active,
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struct i915_request *rq);
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/**
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* i915_active_fence_get - return a reference to the active fence
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* @active - the active tracker
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*
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* i915_active_fence_get() returns a reference to the active fence,
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* or NULL if the active tracker is idle. The reference is obtained under RCU,
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* so no locking is required by the caller.
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*
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* The reference should be freed with dma_fence_put().
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*/
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static inline struct dma_fence *
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i915_active_fence_get(struct i915_active_fence *active)
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{
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struct dma_fence *fence;
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rcu_read_lock();
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fence = dma_fence_get_rcu_safe(&active->fence);
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rcu_read_unlock();
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return fence;
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}
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/**
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* i915_active_fence_isset - report whether the active tracker is assigned
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* @active - the active tracker
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*
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* i915_active_fence_isset() returns true if the active tracker is currently
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* assigned to a fence. Due to the lazy retiring, that fence may be idle
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* and this may report stale information.
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*/
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static inline bool
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i915_active_fence_isset(const struct i915_active_fence *active)
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{
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return rcu_access_pointer(active->fence);
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}
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/*
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* GPU activity tracking
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*
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* Each set of commands submitted to the GPU compromises a single request that
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* signals a fence upon completion. struct i915_request combines the
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* command submission, scheduling and fence signaling roles. If we want to see
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* if a particular task is complete, we need to grab the fence (struct
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* i915_request) for that task and check or wait for it to be signaled. More
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* often though we want to track the status of a bunch of tasks, for example
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* to wait for the GPU to finish accessing some memory across a variety of
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* different command pipelines from different clients. We could choose to
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* track every single request associated with the task, but knowing that
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* each request belongs to an ordered timeline (later requests within a
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* timeline must wait for earlier requests), we need only track the
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* latest request in each timeline to determine the overall status of the
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* task.
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*
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* struct i915_active provides this tracking across timelines. It builds a
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* composite shared-fence, and is updated as new work is submitted to the task,
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* forming a snapshot of the current status. It should be embedded into the
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* different resources that need to track their associated GPU activity to
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* provide a callback when that GPU activity has ceased, or otherwise to
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* provide a serialisation point either for request submission or for CPU
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* synchronisation.
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*/
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void __i915_active_init(struct i915_active *ref,
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int (*active)(struct i915_active *ref),
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void (*retire)(struct i915_active *ref),
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struct lock_class_key *mkey,
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struct lock_class_key *wkey);
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/* Specialise each class of i915_active to avoid impossible lockdep cycles. */
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#define i915_active_init(ref, active, retire) do { \
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static struct lock_class_key __mkey; \
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static struct lock_class_key __wkey; \
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\
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__i915_active_init(ref, active, retire, &__mkey, &__wkey); \
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} while (0)
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int i915_active_ref(struct i915_active *ref,
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struct intel_timeline *tl,
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struct dma_fence *fence);
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static inline int
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i915_active_add_request(struct i915_active *ref, struct i915_request *rq)
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{
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return i915_active_ref(ref, i915_request_timeline(rq), &rq->fence);
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}
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struct dma_fence *
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i915_active_set_exclusive(struct i915_active *ref, struct dma_fence *f);
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static inline bool i915_active_has_exclusive(struct i915_active *ref)
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{
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return rcu_access_pointer(ref->excl.fence);
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}
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int i915_active_wait(struct i915_active *ref);
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int i915_request_await_active(struct i915_request *rq, struct i915_active *ref);
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int i915_active_acquire(struct i915_active *ref);
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bool i915_active_acquire_if_busy(struct i915_active *ref);
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void i915_active_release(struct i915_active *ref);
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static inline void __i915_active_acquire(struct i915_active *ref)
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{
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GEM_BUG_ON(!atomic_read(&ref->count));
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atomic_inc(&ref->count);
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}
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static inline bool
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i915_active_is_idle(const struct i915_active *ref)
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{
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return !atomic_read(&ref->count);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
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void i915_active_fini(struct i915_active *ref);
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#else
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static inline void i915_active_fini(struct i915_active *ref) { }
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#endif
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int i915_active_acquire_preallocate_barrier(struct i915_active *ref,
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struct intel_engine_cs *engine);
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void i915_active_acquire_barrier(struct i915_active *ref);
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void i915_request_add_active_barriers(struct i915_request *rq);
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void i915_active_print(struct i915_active *ref, struct drm_printer *m);
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void i915_active_unlock_wait(struct i915_active *ref);
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#endif /* _I915_ACTIVE_H_ */
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