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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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28707af01b
The commite5e774d883powerpc/fsl-booke: Fix problem with _tlbil_va being interrupted introduce one issue. that casue the problem like this: Kernel BUG at c00b19fc [verbose debug info unavailable] Oops: Exception in kernel mode, sig: 5 [#1] MPC8572 DS Modules linked in: NIP: c00b19fc LR: c00b1c34 CTR: c0064e88 REGS: ef02b7b0 TRAP: 0700 Not tainted (2.6.28-rc8-00057-g1bda712) MSR: 00021000 <ME> CR: 44048028 XER: 20000000 TASK = ef02c000[1] 'init' THREAD: ef02a000 GPR00: 00000001 ef02b860 ef02c000 eec201a0 c0dec2c0 00000000 000078a1 00000400 GPR08: c00b4e40 000078a1 c048ec00 a1780000 44048028 ecd26917 00000001 ef02b948 GPR16: ffffffea 0000020c 00000000 00000000 00000003 0000000a 00000000 000078a1 GPR24: eec201a0 00000000 ed849000 00000400 ef02b95c 00000001 ef02b978 ef02b984 NIP [c00b19fc] __find_get_block+0x24/0x238 LR [c00b1c34] __getblk+0x24/0x2a0 Call Trace: [ef02b860] [c017b768] generic_make_request+0x290/0x328 (unreliable) [ef02b8b0] [c00b1c34] __getblk+0x24/0x2a0 [ef02b910] [c00b4ae4] __bread+0x14/0xf8 [ef02b920] [c00fc228] ext2_get_branch+0xf0/0x138 [ef02b940] [c00fcc88] ext2_get_block+0xb8/0x828 [ef02ba00] [c00bbdc8] do_mpage_readpage+0x188/0x808 [ef02bac0] [c00bc5b4] mpage_readpages+0xec/0x144 [ef02bb50] [c00fba38] ext2_readpages+0x24/0x34 [ef02bb60] [c006ade0] __do_page_cache_readahead+0x150/0x230 [ef02bbb0] [c0064bdc] filemap_fault+0x31c/0x3e0 [ef02bbf0] [c00728b8] __do_fault+0x60/0x5b0 [ef02bc50] [c0011e0c] do_page_fault+0x2d8/0x4c4 [ef02bd10] [c000ed90] handle_page_fault+0xc/0x80 [ef02bdd0] [c00c7adc] set_brk+0x74/0x9c [ef02bdf0] [c00c9274] load_elf_binary+0x70c/0x1180 [ef02be70] [c00945f0] search_binary_handler+0xa8/0x274 [ef02bea0] [c0095818] do_execve+0x19c/0x1d4 [ef02bed0] [c000766c] sys_execve+0x58/0x84 [ef02bef0] [c000e950] ret_from_syscall+0x0/0x3c [ef02bfb0] [c009c6fc] sys_dup+0x24/0x6c [ef02bfc0] [c0001e04] init_post+0xb0/0xf0 [ef02bfd0] [c046c1ac] kernel_init+0xcc/0xf4 [ef02bff0] [c000e6d0] kernel_thread+0x4c/0x68 Instruction dump: 4bffffa4 813f000c 4bffffac 9421ffb0 7c0802a6 7d800026 90010054 bf210034 91810030 7c0000a6 68008000 54008ffe <0f000000> 3d20c04e 3b29ffb8 38000008 The issue was the beqlr returns early but we haven't reenabled interrupts. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1040 lines
21 KiB
ArmAsm
1040 lines
21 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* kexec bits:
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* Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
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* GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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#include <asm/mmu.h>
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#include <asm/ppc_asm.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/processor.h>
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#include <asm/kexec.h>
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.text
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#ifdef CONFIG_IRQSTACKS
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_GLOBAL(call_do_softirq)
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mflr r0
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stw r0,4(r1)
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
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mr r1,r3
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bl __do_softirq
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lwz r1,0(r1)
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lwz r0,4(r1)
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mtlr r0
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blr
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_GLOBAL(call_handle_irq)
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mflr r0
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stw r0,4(r1)
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mtctr r6
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stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r5)
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mr r1,r5
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bctrl
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lwz r1,0(r1)
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lwz r0,4(r1)
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mtlr r0
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blr
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#endif /* CONFIG_IRQSTACKS */
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/*
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* This returns the high 64 bits of the product of two 64-bit numbers.
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*/
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_GLOBAL(mulhdu)
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cmpwi r6,0
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cmpwi cr1,r3,0
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mr r10,r4
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mulhwu r4,r4,r5
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beq 1f
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mulhwu r0,r10,r6
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mullw r7,r10,r5
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addc r7,r0,r7
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addze r4,r4
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1: beqlr cr1 /* all done if high part of A is 0 */
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mr r10,r3
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mullw r9,r3,r5
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mulhwu r3,r3,r5
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beq 2f
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mullw r0,r10,r6
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mulhwu r8,r10,r6
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addc r7,r0,r7
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adde r4,r4,r8
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addze r3,r3
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2: addc r4,r4,r9
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addze r3,r3
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blr
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/*
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* sub_reloc_offset(x) returns x - reloc_offset().
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*/
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_GLOBAL(sub_reloc_offset)
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mflr r0
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bl 1f
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1: mflr r5
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r5,r4,r5
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subf r3,r5,r3
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mtlr r0
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blr
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/*
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* reloc_got2 runs through the .got2 section adding an offset
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* to each entry.
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*/
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_GLOBAL(reloc_got2)
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mflr r11
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lis r7,__got2_start@ha
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addi r7,r7,__got2_start@l
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lis r8,__got2_end@ha
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addi r8,r8,__got2_end@l
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subf r8,r7,r8
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srwi. r8,r8,2
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beqlr
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mtctr r8
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bl 1f
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1: mflr r0
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lis r4,1b@ha
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addi r4,r4,1b@l
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subf r0,r4,r0
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add r7,r0,r7
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2: lwz r0,0(r7)
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add r0,r0,r3
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stw r0,0(r7)
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addi r7,r7,4
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bdnz 2b
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mtlr r11
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blr
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/*
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* call_setup_cpu - call the setup_cpu function for this cpu
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* r3 = data offset, r24 = cpu number
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*
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* Setup function is called with:
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* r3 = data offset
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* r4 = ptr to CPU spec (relocated)
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*/
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_GLOBAL(call_setup_cpu)
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addis r4,r3,cur_cpu_spec@ha
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addi r4,r4,cur_cpu_spec@l
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lwz r4,0(r4)
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add r4,r4,r3
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lwz r5,CPU_SPEC_SETUP(r4)
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cmpwi 0,r5,0
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add r5,r5,r3
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beqlr
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mtctr r5
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bctr
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#if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_6xx)
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/* This gets called by via-pmu.c to switch the PLL selection
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* on 750fx CPU. This function should really be moved to some
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* other place (as most of the cpufreq code in via-pmu
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*/
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_GLOBAL(low_choose_750fx_pll)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* If switching to PLL1, disable HID0:BTIC */
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cmplwi cr0,r3,0
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beq 1f
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mfspr r5,SPRN_HID0
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rlwinm r5,r5,0,27,25
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
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rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
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rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
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or r4,r4,r5
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mtspr SPRN_HID1,r4
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/* Store new HID1 image */
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rlwinm r6,r1,0,0,(31-THREAD_SHIFT)
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lwz r6,TI_CPU(r6)
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slwi r6,r6,2
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addis r6,r6,nap_save_hid1@ha
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stw r4,nap_save_hid1@l(r6)
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/* If switching to PLL0, enable HID0:BTIC */
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cmplwi cr0,r3,0
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bne 1f
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mfspr r5,SPRN_HID0
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ori r5,r5,HID0_BTIC
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sync
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mtspr SPRN_HID0,r5
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isync
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sync
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1:
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/* Return */
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mtmsr r7
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blr
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_GLOBAL(low_choose_7447a_dfs)
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/* Clear MSR:EE */
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mfmsr r7
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rlwinm r0,r7,0,17,15
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mtmsr r0
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/* Calc new HID1 value */
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mfspr r4,SPRN_HID1
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insrwi r4,r3,1,9 /* insert parameter into bit 9 */
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sync
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mtspr SPRN_HID1,r4
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sync
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isync
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/* Return */
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mtmsr r7
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blr
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#endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_6xx */
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/*
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* complement mask on the msr then "or" some values on.
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* _nmask_and_or_msr(nmask, value_to_or)
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*/
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_GLOBAL(_nmask_and_or_msr)
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mfmsr r0 /* Get current msr */
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andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
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or r0,r0,r4 /* Or on the bits in r4 (second parm) */
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SYNC /* Some chip revs have problems here... */
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mtmsr r0 /* Update machine state */
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isync
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blr /* Done */
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#ifdef CONFIG_40x
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_readb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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lbz r3,0(r3)
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sync
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mtmsr r7
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sync
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isync
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blr
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/*
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* Do an IO access in real mode
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*/
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_GLOBAL(real_writeb)
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mfmsr r7
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ori r0,r7,MSR_DR
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xori r0,r0,MSR_DR
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sync
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mtmsr r0
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sync
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isync
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stb r3,0(r4)
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sync
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mtmsr r7
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sync
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isync
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blr
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#endif /* CONFIG_40x */
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/*
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* Flush MMU TLB
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_all)
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_GLOBAL(_tlbil_pid)
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#endif
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_GLOBAL(_tlbia)
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#if defined(CONFIG_40x)
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sync /* Flush to memory before changing mapping */
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tlbia
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isync /* Flush shadow TLB */
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#elif defined(CONFIG_44x)
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li r3,0
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sync
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/* Load high watermark */
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lis r4,tlb_44x_hwater@ha
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lwz r5,tlb_44x_hwater@l(r4)
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1: tlbwe r3,r3,PPC44x_TLB_PAGEID
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addi r3,r3,1
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cmpw 0,r3,r5
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ble 1b
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isync
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#elif defined(CONFIG_FSL_BOOKE)
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/* Invalidate all entries in TLB0 */
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li r3, 0x04
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tlbivax 0,3
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/* Invalidate all entries in TLB1 */
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li r3, 0x0c
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tlbivax 0,3
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msync
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#ifdef CONFIG_SMP
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,10
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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sync
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tlbia
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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sync
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tlbia
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! defined(CONFIG_40x) */
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blr
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/*
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* Flush MMU TLB for a particular address
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*/
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#ifndef CONFIG_FSL_BOOKE
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_GLOBAL(_tlbil_va)
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#endif
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_GLOBAL(_tlbie)
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#if defined(CONFIG_40x)
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/* We run the search with interrupts disabled because we have to change
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* the PID and I don't want to preempt when that happens.
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*/
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mfmsr r5
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mfspr r6,SPRN_PID
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wrteei 0
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mtspr SPRN_PID,r4
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tlbsx. r3, 0, r3
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mtspr SPRN_PID,r6
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wrtee r5
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
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* Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
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* the TLB entry. */
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tlbwe r3, r3, TLB_TAG
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isync
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10:
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#elif defined(CONFIG_44x)
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mfspr r5,SPRN_MMUCR
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rlwimi r5,r4,0,24,31 /* Set TID */
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/* We have to run the search with interrupts disabled, even critical
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* and debug interrupts (in fact the only critical exceptions we have
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* are debug and machine check). Otherwise an interrupt which causes
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* a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
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mfmsr r4
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lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
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addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
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andc r6,r4,r6
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mtmsr r6
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mtspr SPRN_MMUCR,r5
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tlbsx. r3, 0, r3
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mtmsr r4
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bne 10f
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sync
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/* There are only 64 TLB entries, so r3 < 64,
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* which means bit 22, is clear. Since 22 is
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* the V bit in the TLB_PAGEID, loading this
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* value will invalidate the TLB entry.
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*/
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tlbwe r3, r3, PPC44x_TLB_PAGEID
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isync
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10:
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#elif defined(CONFIG_FSL_BOOKE)
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rlwinm r4, r3, 0, 0, 19
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ori r5, r4, 0x08 /* TLBSEL = 1 */
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tlbivax 0, r4
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tlbivax 0, r5
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msync
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#if defined(CONFIG_SMP)
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tlbsync
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#endif /* CONFIG_SMP */
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#else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
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#if defined(CONFIG_SMP)
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rlwinm r8,r1,0,0,(31-THREAD_SHIFT)
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lwz r8,TI_CPU(r8)
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oris r8,r8,11
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mfmsr r10
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SYNC
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rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
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rlwinm r0,r0,0,28,26 /* clear DR */
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mtmsr r0
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SYNC_601
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isync
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lis r9,mmu_hash_lock@h
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ori r9,r9,mmu_hash_lock@l
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tophys(r9,r9)
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10: lwarx r7,0,r9
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cmpwi 0,r7,0
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bne- 10b
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stwcx. r8,0,r9
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bne- 10b
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eieio
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tlbie r3
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sync
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TLBSYNC
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li r0,0
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stw r0,0(r9) /* clear mmu_hash_lock */
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mtmsr r10
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SYNC_601
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isync
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#else /* CONFIG_SMP */
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tlbie r3
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sync
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#endif /* CONFIG_SMP */
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#endif /* ! CONFIG_40x */
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blr
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#if defined(CONFIG_FSL_BOOKE)
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/*
|
|
* Flush MMU TLB, but only on the local processor (no broadcast)
|
|
*/
|
|
_GLOBAL(_tlbil_all)
|
|
#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
|
|
MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
|
|
li r3,(MMUCSR0_TLBFI)@l
|
|
mtspr SPRN_MMUCSR0, r3
|
|
1:
|
|
mfspr r3,SPRN_MMUCSR0
|
|
andi. r3,r3,MMUCSR0_TLBFI@l
|
|
bne 1b
|
|
blr
|
|
|
|
/*
|
|
* Flush MMU TLB for a particular process id, but only on the local processor
|
|
* (no broadcast)
|
|
*/
|
|
_GLOBAL(_tlbil_pid)
|
|
/* we currently do an invalidate all since we don't have per pid invalidate */
|
|
li r3,(MMUCSR0_TLBFI)@l
|
|
mtspr SPRN_MMUCSR0, r3
|
|
1:
|
|
mfspr r3,SPRN_MMUCSR0
|
|
andi. r3,r3,MMUCSR0_TLBFI@l
|
|
bne 1b
|
|
msync
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Flush MMU TLB for a particular address, but only on the local processor
|
|
* (no broadcast)
|
|
*/
|
|
_GLOBAL(_tlbil_va)
|
|
mfmsr r10
|
|
wrteei 0
|
|
slwi r4,r4,16
|
|
mtspr SPRN_MAS6,r4 /* assume AS=0 for now */
|
|
tlbsx 0,r3
|
|
mfspr r4,SPRN_MAS1 /* check valid */
|
|
andis. r3,r4,MAS1_VALID@h
|
|
beq 1f
|
|
rlwinm r4,r4,0,1,31
|
|
mtspr SPRN_MAS1,r4
|
|
tlbwe
|
|
msync
|
|
isync
|
|
1: wrtee r10
|
|
blr
|
|
#endif /* CONFIG_FSL_BOOKE */
|
|
|
|
|
|
/*
|
|
* Flush instruction cache.
|
|
* This is a no-op on the 601.
|
|
*/
|
|
_GLOBAL(flush_instruction_cache)
|
|
#if defined(CONFIG_8xx)
|
|
isync
|
|
lis r5, IDC_INVALL@h
|
|
mtspr SPRN_IC_CST, r5
|
|
#elif defined(CONFIG_4xx)
|
|
#ifdef CONFIG_403GCX
|
|
li r3, 512
|
|
mtctr r3
|
|
lis r4, KERNELBASE@h
|
|
1: iccci 0, r4
|
|
addi r4, r4, 16
|
|
bdnz 1b
|
|
#else
|
|
lis r3, KERNELBASE@h
|
|
iccci 0,r3
|
|
#endif
|
|
#elif CONFIG_FSL_BOOKE
|
|
BEGIN_FTR_SECTION
|
|
mfspr r3,SPRN_L1CSR0
|
|
ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
|
|
/* msync; isync recommended here */
|
|
mtspr SPRN_L1CSR0,r3
|
|
isync
|
|
blr
|
|
END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
|
|
mfspr r3,SPRN_L1CSR1
|
|
ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
|
|
mtspr SPRN_L1CSR1,r3
|
|
#else
|
|
mfspr r3,SPRN_PVR
|
|
rlwinm r3,r3,16,16,31
|
|
cmpwi 0,r3,1
|
|
beqlr /* for 601, do nothing */
|
|
/* 603/604 processor - use invalidate-all bit in HID0 */
|
|
mfspr r3,SPRN_HID0
|
|
ori r3,r3,HID0_ICFI
|
|
mtspr SPRN_HID0,r3
|
|
#endif /* CONFIG_8xx/4xx */
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Write any modified data cache blocks out to memory
|
|
* and invalidate the corresponding instruction cache blocks.
|
|
* This is a no-op on the 601.
|
|
*
|
|
* flush_icache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_KPROBE(__flush_icache_range)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
mr r6,r3
|
|
1: dcbst 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
mtctr r4
|
|
2: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 2b
|
|
sync /* additional sync needed on g4 */
|
|
isync
|
|
blr
|
|
/*
|
|
* Write any modified data cache blocks out to memory.
|
|
* Does not invalidate the corresponding cache lines (especially for
|
|
* any corresponding instruction cache).
|
|
*
|
|
* clean_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(clean_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbst 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
blr
|
|
|
|
/*
|
|
* Write any modified data cache blocks out to memory and invalidate them.
|
|
* Does not invalidate the corresponding instruction cache blocks.
|
|
*
|
|
* flush_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(flush_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbf 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbst's to get to ram */
|
|
blr
|
|
|
|
/*
|
|
* Like above, but invalidate the D-cache. This is used by the 8xx
|
|
* to invalidate the cache so the PPC core doesn't get stale data
|
|
* from the CPM (no cache snooping here :-).
|
|
*
|
|
* invalidate_dcache_range(unsigned long start, unsigned long stop)
|
|
*/
|
|
_GLOBAL(invalidate_dcache_range)
|
|
li r5,L1_CACHE_BYTES-1
|
|
andc r3,r3,r5
|
|
subf r4,r3,r4
|
|
add r4,r4,r5
|
|
srwi. r4,r4,L1_CACHE_SHIFT
|
|
beqlr
|
|
mtctr r4
|
|
|
|
1: dcbi 0,r3
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync /* wait for dcbi's to get to ram */
|
|
blr
|
|
|
|
/*
|
|
* Flush a particular page from the data cache to RAM.
|
|
* Note: this is necessary because the instruction cache does *not*
|
|
* snoop from the data cache.
|
|
* This is a no-op on the 601 which has a unified cache.
|
|
*
|
|
* void __flush_dcache_icache(void *page)
|
|
*/
|
|
_GLOBAL(__flush_dcache_icache)
|
|
BEGIN_FTR_SECTION
|
|
blr
|
|
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
|
mtctr r4
|
|
mr r6,r3
|
|
0: dcbst 0,r3 /* Write line to ram */
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 0b
|
|
sync
|
|
#ifndef CONFIG_44x
|
|
/* We don't flush the icache on 44x. Those have a virtual icache
|
|
* and we don't have access to the virtual address here (it's
|
|
* not the page vaddr but where it's mapped in user space). The
|
|
* flushing of the icache on these is handled elsewhere, when
|
|
* a change in the address space occurs, before returning to
|
|
* user space
|
|
*/
|
|
mtctr r4
|
|
1: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync
|
|
isync
|
|
#endif /* CONFIG_44x */
|
|
blr
|
|
|
|
/*
|
|
* Flush a particular page from the data cache to RAM, identified
|
|
* by its physical address. We turn off the MMU so we can just use
|
|
* the physical address (this may be a highmem page without a kernel
|
|
* mapping).
|
|
*
|
|
* void __flush_dcache_icache_phys(unsigned long physaddr)
|
|
*/
|
|
_GLOBAL(__flush_dcache_icache_phys)
|
|
BEGIN_FTR_SECTION
|
|
blr /* for 601, do nothing */
|
|
END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
|
|
mfmsr r10
|
|
rlwinm r0,r10,0,28,26 /* clear DR */
|
|
mtmsr r0
|
|
isync
|
|
rlwinm r3,r3,0,0,19 /* Get page base address */
|
|
li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
|
|
mtctr r4
|
|
mr r6,r3
|
|
0: dcbst 0,r3 /* Write line to ram */
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 0b
|
|
sync
|
|
mtctr r4
|
|
1: icbi 0,r6
|
|
addi r6,r6,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
sync
|
|
mtmsr r10 /* restore DR */
|
|
isync
|
|
blr
|
|
|
|
/*
|
|
* Clear pages using the dcbz instruction, which doesn't cause any
|
|
* memory traffic (except to write out any cache lines which get
|
|
* displaced). This only works on cacheable memory.
|
|
*
|
|
* void clear_pages(void *page, int order) ;
|
|
*/
|
|
_GLOBAL(clear_pages)
|
|
li r0,4096/L1_CACHE_BYTES
|
|
slw r0,r0,r4
|
|
mtctr r0
|
|
#ifdef CONFIG_8xx
|
|
li r4, 0
|
|
1: stw r4, 0(r3)
|
|
stw r4, 4(r3)
|
|
stw r4, 8(r3)
|
|
stw r4, 12(r3)
|
|
#else
|
|
1: dcbz 0,r3
|
|
#endif
|
|
addi r3,r3,L1_CACHE_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
/*
|
|
* Copy a whole page. We use the dcbz instruction on the destination
|
|
* to reduce memory traffic (it eliminates the unnecessary reads of
|
|
* the destination into cache). This requires that the destination
|
|
* is cacheable.
|
|
*/
|
|
#define COPY_16_BYTES \
|
|
lwz r6,4(r4); \
|
|
lwz r7,8(r4); \
|
|
lwz r8,12(r4); \
|
|
lwzu r9,16(r4); \
|
|
stw r6,4(r3); \
|
|
stw r7,8(r3); \
|
|
stw r8,12(r3); \
|
|
stwu r9,16(r3)
|
|
|
|
_GLOBAL(copy_page)
|
|
addi r3,r3,-4
|
|
addi r4,r4,-4
|
|
|
|
#ifdef CONFIG_8xx
|
|
/* don't use prefetch on 8xx */
|
|
li r0,4096/L1_CACHE_BYTES
|
|
mtctr r0
|
|
1: COPY_16_BYTES
|
|
bdnz 1b
|
|
blr
|
|
|
|
#else /* not 8xx, we can prefetch */
|
|
li r5,4
|
|
|
|
#if MAX_COPY_PREFETCH > 1
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
mtctr r0
|
|
11: dcbt r11,r4
|
|
addi r11,r11,L1_CACHE_BYTES
|
|
bdnz 11b
|
|
#else /* MAX_COPY_PREFETCH == 1 */
|
|
dcbt r5,r4
|
|
li r11,L1_CACHE_BYTES+4
|
|
#endif /* MAX_COPY_PREFETCH */
|
|
li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
|
|
crclr 4*cr0+eq
|
|
2:
|
|
mtctr r0
|
|
1:
|
|
dcbt r11,r4
|
|
dcbz r5,r3
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 32
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 64
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#if L1_CACHE_BYTES >= 128
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
COPY_16_BYTES
|
|
#endif
|
|
#endif
|
|
#endif
|
|
bdnz 1b
|
|
beqlr
|
|
crnot 4*cr0+eq,4*cr0+eq
|
|
li r0,MAX_COPY_PREFETCH
|
|
li r11,4
|
|
b 2b
|
|
#endif /* CONFIG_8xx */
|
|
|
|
/*
|
|
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
|
|
* void atomic_set_mask(atomic_t mask, atomic_t *addr);
|
|
*/
|
|
_GLOBAL(atomic_clear_mask)
|
|
10: lwarx r5,0,r4
|
|
andc r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
_GLOBAL(atomic_set_mask)
|
|
10: lwarx r5,0,r4
|
|
or r5,r5,r3
|
|
PPC405_ERR77(0,r4)
|
|
stwcx. r5,0,r4
|
|
bne- 10b
|
|
blr
|
|
|
|
/*
|
|
* Extended precision shifts.
|
|
*
|
|
* Updated to be valid for shift counts from 0 to 63 inclusive.
|
|
* -- Gabriel
|
|
*
|
|
* R3/R4 has 64 bit value
|
|
* R5 has shift count
|
|
* result in R3/R4
|
|
*
|
|
* ashrdi3: arithmetic right shift (sign propagation)
|
|
* lshrdi3: logical right shift
|
|
* ashldi3: left shift
|
|
*/
|
|
_GLOBAL(__ashrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
|
|
sraw r7,r3,r7 # t2 = MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
|
|
sraw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__ashldi3)
|
|
subfic r6,r5,32
|
|
slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
|
|
slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
|
|
or r3,r3,r6 # MSW |= t1
|
|
slw r4,r4,r5 # LSW = LSW << count
|
|
or r3,r3,r7 # MSW |= t2
|
|
blr
|
|
|
|
_GLOBAL(__lshrdi3)
|
|
subfic r6,r5,32
|
|
srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
|
|
addi r7,r5,32 # could be xori, or addi with -32
|
|
slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
|
|
srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
|
|
or r4,r4,r6 # LSW |= t1
|
|
srw r3,r3,r5 # MSW = MSW >> count
|
|
or r4,r4,r7 # LSW |= t2
|
|
blr
|
|
|
|
/*
|
|
* 64-bit comparison: __ucmpdi2(u64 a, u64 b)
|
|
* Returns 0 if a < b, 1 if a == b, 2 if a > b.
|
|
*/
|
|
_GLOBAL(__ucmpdi2)
|
|
cmplw r3,r5
|
|
li r3,1
|
|
bne 1f
|
|
cmplw r4,r6
|
|
beqlr
|
|
1: li r3,0
|
|
bltlr
|
|
li r3,2
|
|
blr
|
|
|
|
_GLOBAL(abs)
|
|
srawi r4,r3,31
|
|
xor r3,r3,r4
|
|
sub r3,r3,r4
|
|
blr
|
|
|
|
/*
|
|
* Create a kernel thread
|
|
* kernel_thread(fn, arg, flags)
|
|
*/
|
|
_GLOBAL(kernel_thread)
|
|
stwu r1,-16(r1)
|
|
stw r30,8(r1)
|
|
stw r31,12(r1)
|
|
mr r30,r3 /* function */
|
|
mr r31,r4 /* argument */
|
|
ori r3,r5,CLONE_VM /* flags */
|
|
oris r3,r3,CLONE_UNTRACED>>16
|
|
li r4,0 /* new sp (unused) */
|
|
li r0,__NR_clone
|
|
sc
|
|
bns+ 1f /* did system call indicate error? */
|
|
neg r3,r3 /* if so, make return code negative */
|
|
1: cmpwi 0,r3,0 /* parent or child? */
|
|
bne 2f /* return if parent */
|
|
li r0,0 /* make top-level stack frame */
|
|
stwu r0,-16(r1)
|
|
mtlr r30 /* fn addr in lr */
|
|
mr r3,r31 /* load arg and call fn */
|
|
PPC440EP_ERR42
|
|
blrl
|
|
li r0,__NR_exit /* exit if function returns */
|
|
li r3,0
|
|
sc
|
|
2: lwz r30,8(r1)
|
|
lwz r31,12(r1)
|
|
addi r1,r1,16
|
|
blr
|
|
|
|
/*
|
|
* This routine is just here to keep GCC happy - sigh...
|
|
*/
|
|
_GLOBAL(__main)
|
|
blr
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
/*
|
|
* Must be relocatable PIC code callable as a C function.
|
|
*/
|
|
.globl relocate_new_kernel
|
|
relocate_new_kernel:
|
|
/* r3 = page_list */
|
|
/* r4 = reboot_code_buffer */
|
|
/* r5 = start_address */
|
|
|
|
li r0, 0
|
|
|
|
/*
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|
* Set Machine Status Register to a known status,
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|
* switch the MMU off and jump to 1: in a single step.
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|
*/
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|
|
|
mr r8, r0
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|
ori r8, r8, MSR_RI|MSR_ME
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|
mtspr SPRN_SRR1, r8
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|
addi r8, r4, 1f - relocate_new_kernel
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|
mtspr SPRN_SRR0, r8
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|
sync
|
|
rfi
|
|
|
|
1:
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|
/* from this point address translation is turned off */
|
|
/* and interrupts are disabled */
|
|
|
|
/* set a new stack at the bottom of our page... */
|
|
/* (not really needed now) */
|
|
addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
|
|
stw r0, 0(r1)
|
|
|
|
/* Do the copies */
|
|
li r6, 0 /* checksum */
|
|
mr r0, r3
|
|
b 1f
|
|
|
|
0: /* top, read another word for the indirection page */
|
|
lwzu r0, 4(r3)
|
|
|
|
1:
|
|
/* is it a destination page? (r8) */
|
|
rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
|
|
beq 2f
|
|
|
|
rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
b 0b
|
|
|
|
2: /* is it an indirection page? (r3) */
|
|
rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
|
|
beq 2f
|
|
|
|
rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
subi r3, r3, 4
|
|
b 0b
|
|
|
|
2: /* are we done? */
|
|
rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
|
|
beq 2f
|
|
b 3f
|
|
|
|
2: /* is it a source page? (r9) */
|
|
rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
|
|
beq 0b
|
|
|
|
rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
|
|
|
|
li r7, PAGE_SIZE / 4
|
|
mtctr r7
|
|
subi r9, r9, 4
|
|
subi r8, r8, 4
|
|
9:
|
|
lwzu r0, 4(r9) /* do the copy */
|
|
xor r6, r6, r0
|
|
stwu r0, 4(r8)
|
|
dcbst 0, r8
|
|
sync
|
|
icbi 0, r8
|
|
bdnz 9b
|
|
|
|
addi r9, r9, 4
|
|
addi r8, r8, 4
|
|
b 0b
|
|
|
|
3:
|
|
|
|
/* To be certain of avoiding problems with self-modifying code
|
|
* execute a serializing instruction here.
|
|
*/
|
|
isync
|
|
sync
|
|
|
|
/* jump to the entry point, usually the setup routine */
|
|
mtlr r5
|
|
blrl
|
|
|
|
1: b 1b
|
|
|
|
relocate_new_kernel_end:
|
|
|
|
.globl relocate_new_kernel_size
|
|
relocate_new_kernel_size:
|
|
.long relocate_new_kernel_end - relocate_new_kernel
|
|
#endif
|