mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 01:45:23 +07:00
dcf5907e0e
The Qualcomm SPMI GPIO and MPP lines are problematic: the
are fetched from the main MFD driver with platform_get_irq()
which means that at this point they will all be assigned the
flags set up for the interrupts in the device tree.
That is problematic since these are flagged as rising edge
and an this point the interrupt descriptor is assigned a
rising edge, while the only thing the GPIO/MPP drivers really
do is issue irq_get_irqchip_state() on the line to read it
out and to provide a .to_irq() helper for *other* IRQ
consumers.
If another device tree node tries to flag the same IRQ
for use as something else than rising edge, the kernel
irqdomain core will protest like this:
type mismatch, failed to map hwirq-NN for <FOO>!
Which is what happens when the device tree defines two
contradictory flags for the same interrupt line.
To work around this and alleviate the problem, assign 0
as flag for the interrupts taken by the PM GPIO and MPP
drivers. This will lead to the flag being unset, and a
second consumer requesting rising, falling, both or level
interrupts will be respected. This is what the qcom-pm*.dtsi
files already do.
Switched to using the symbolic name IRQ_TYPE_NONE so that
we get this more readable.
This misconfiguration was caused by a copy/pasting the
APQ8064 set-up, the latter has been fixed in a separate
patch.
Tested with one of the SPMI GPIOs: after this I can
successfully request one of these GPIOs as falling edge
from the device tree.
Fixes: 0840ea9e44 ("ARM: dts: add GPIO and MPP to MSM8660 PMIC")
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Björn Andersson <bjorn.andersson@linaro.org>
Cc: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
417 lines
9.5 KiB
Plaintext
417 lines
9.5 KiB
Plaintext
/dts-v1/;
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/qcom,gcc-msm8660.h>
|
|
#include <dt-bindings/soc/qcom,gsbi.h>
|
|
|
|
/ {
|
|
model = "Qualcomm MSM8660";
|
|
compatible = "qcom,msm8660";
|
|
interrupt-parent = <&intc>;
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
compatible = "qcom,scorpion";
|
|
enable-method = "qcom,gcc-msm8660";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
cpu@1 {
|
|
compatible = "qcom,scorpion";
|
|
enable-method = "qcom,gcc-msm8660";
|
|
device_type = "cpu";
|
|
reg = <1>;
|
|
next-level-cache = <&L2>;
|
|
};
|
|
|
|
L2: l2-cache {
|
|
compatible = "cache";
|
|
cache-level = <2>;
|
|
};
|
|
};
|
|
|
|
cpu-pmu {
|
|
compatible = "qcom,scorpion-mp-pmu";
|
|
interrupts = <1 9 0x304>;
|
|
};
|
|
|
|
clocks {
|
|
cxo_board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
pxo_board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <27000000>;
|
|
};
|
|
|
|
sleep_clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
};
|
|
|
|
soc: soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@2080000 {
|
|
compatible = "qcom,msm-8660-qgic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
reg = < 0x02080000 0x1000 >,
|
|
< 0x02081000 0x1000 >;
|
|
};
|
|
|
|
timer@2000000 {
|
|
compatible = "qcom,scss-timer", "qcom,msm-timer";
|
|
interrupts = <1 0 0x301>,
|
|
<1 1 0x301>,
|
|
<1 2 0x301>;
|
|
reg = <0x02000000 0x100>;
|
|
clock-frequency = <27000000>,
|
|
<32768>;
|
|
cpu-offset = <0x40000>;
|
|
};
|
|
|
|
tlmm: pinctrl@800000 {
|
|
compatible = "qcom,msm8660-pinctrl";
|
|
reg = <0x800000 0x4000>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupts = <0 16 0x4>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
|
|
};
|
|
|
|
gcc: clock-controller@900000 {
|
|
compatible = "qcom,gcc-msm8660";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
reg = <0x900000 0x4000>;
|
|
};
|
|
|
|
gsbi12: gsbi@19c00000 {
|
|
compatible = "qcom,gsbi-v1.0.0";
|
|
cell-index = <12>;
|
|
reg = <0x19c00000 0x100>;
|
|
clocks = <&gcc GSBI12_H_CLK>;
|
|
clock-names = "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
syscon-tcsr = <&tcsr>;
|
|
|
|
gsbi12_serial: serial@19c40000 {
|
|
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
|
reg = <0x19c40000 0x1000>,
|
|
<0x19c00000 0x1000>;
|
|
interrupts = <0 195 IRQ_TYPE_NONE>;
|
|
clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
status = "disabled";
|
|
};
|
|
|
|
gsbi12_i2c: i2c@19c80000 {
|
|
compatible = "qcom,i2c-qup-v1.1.1";
|
|
reg = <0x19c80000 0x1000>;
|
|
interrupts = <0 196 IRQ_TYPE_NONE>;
|
|
clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
|
|
clock-names = "core", "iface";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
qcom,ssbi@500000 {
|
|
compatible = "qcom,ssbi";
|
|
reg = <0x500000 0x1000>;
|
|
qcom,controller-type = "pmic-arbiter";
|
|
|
|
pmicintc: pmic@0 {
|
|
compatible = "qcom,pm8058";
|
|
interrupt-parent = <&tlmm>;
|
|
interrupts = <88 8>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
pm8058_gpio: gpio@150 {
|
|
compatible = "qcom,pm8058-gpio",
|
|
"qcom,ssbi-gpio";
|
|
reg = <0x150>;
|
|
interrupt-parent = <&pmicintc>;
|
|
interrupts = <192 IRQ_TYPE_NONE>,
|
|
<193 IRQ_TYPE_NONE>,
|
|
<194 IRQ_TYPE_NONE>,
|
|
<195 IRQ_TYPE_NONE>,
|
|
<196 IRQ_TYPE_NONE>,
|
|
<197 IRQ_TYPE_NONE>,
|
|
<198 IRQ_TYPE_NONE>,
|
|
<199 IRQ_TYPE_NONE>,
|
|
<200 IRQ_TYPE_NONE>,
|
|
<201 IRQ_TYPE_NONE>,
|
|
<202 IRQ_TYPE_NONE>,
|
|
<203 IRQ_TYPE_NONE>,
|
|
<204 IRQ_TYPE_NONE>,
|
|
<205 IRQ_TYPE_NONE>,
|
|
<206 IRQ_TYPE_NONE>,
|
|
<207 IRQ_TYPE_NONE>,
|
|
<208 IRQ_TYPE_NONE>,
|
|
<209 IRQ_TYPE_NONE>,
|
|
<210 IRQ_TYPE_NONE>,
|
|
<211 IRQ_TYPE_NONE>,
|
|
<212 IRQ_TYPE_NONE>,
|
|
<213 IRQ_TYPE_NONE>,
|
|
<214 IRQ_TYPE_NONE>,
|
|
<215 IRQ_TYPE_NONE>,
|
|
<216 IRQ_TYPE_NONE>,
|
|
<217 IRQ_TYPE_NONE>,
|
|
<218 IRQ_TYPE_NONE>,
|
|
<219 IRQ_TYPE_NONE>,
|
|
<220 IRQ_TYPE_NONE>,
|
|
<221 IRQ_TYPE_NONE>,
|
|
<222 IRQ_TYPE_NONE>,
|
|
<223 IRQ_TYPE_NONE>,
|
|
<224 IRQ_TYPE_NONE>,
|
|
<225 IRQ_TYPE_NONE>,
|
|
<226 IRQ_TYPE_NONE>,
|
|
<227 IRQ_TYPE_NONE>,
|
|
<228 IRQ_TYPE_NONE>,
|
|
<229 IRQ_TYPE_NONE>,
|
|
<230 IRQ_TYPE_NONE>,
|
|
<231 IRQ_TYPE_NONE>,
|
|
<232 IRQ_TYPE_NONE>,
|
|
<233 IRQ_TYPE_NONE>,
|
|
<234 IRQ_TYPE_NONE>,
|
|
<235 IRQ_TYPE_NONE>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
};
|
|
|
|
pm8058_mpps: mpps@50 {
|
|
compatible = "qcom,pm8058-mpp",
|
|
"qcom,ssbi-mpp";
|
|
reg = <0x50>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-parent = <&pmicintc>;
|
|
interrupts =
|
|
<128 IRQ_TYPE_NONE>,
|
|
<129 IRQ_TYPE_NONE>,
|
|
<130 IRQ_TYPE_NONE>,
|
|
<131 IRQ_TYPE_NONE>,
|
|
<132 IRQ_TYPE_NONE>,
|
|
<133 IRQ_TYPE_NONE>,
|
|
<134 IRQ_TYPE_NONE>,
|
|
<135 IRQ_TYPE_NONE>,
|
|
<136 IRQ_TYPE_NONE>,
|
|
<137 IRQ_TYPE_NONE>,
|
|
<138 IRQ_TYPE_NONE>,
|
|
<139 IRQ_TYPE_NONE>;
|
|
};
|
|
|
|
pwrkey@1c {
|
|
compatible = "qcom,pm8058-pwrkey";
|
|
reg = <0x1c>;
|
|
interrupt-parent = <&pmicintc>;
|
|
interrupts = <50 1>, <51 1>;
|
|
debounce = <15625>;
|
|
pull-up;
|
|
};
|
|
|
|
keypad@148 {
|
|
compatible = "qcom,pm8058-keypad";
|
|
reg = <0x148>;
|
|
interrupt-parent = <&pmicintc>;
|
|
interrupts = <74 1>, <75 1>;
|
|
debounce = <15>;
|
|
scan-delay = <32>;
|
|
row-hold = <91500>;
|
|
};
|
|
|
|
rtc@1e8 {
|
|
compatible = "qcom,pm8058-rtc";
|
|
reg = <0x1e8>;
|
|
interrupt-parent = <&pmicintc>;
|
|
interrupts = <39 1>;
|
|
allow-set-time;
|
|
};
|
|
|
|
vibrator@4a {
|
|
compatible = "qcom,pm8058-vib";
|
|
reg = <0x4a>;
|
|
};
|
|
};
|
|
};
|
|
|
|
l2cc: clock-controller@2082000 {
|
|
compatible = "syscon";
|
|
reg = <0x02082000 0x1000>;
|
|
};
|
|
|
|
rpm: rpm@104000 {
|
|
compatible = "qcom,rpm-msm8660";
|
|
reg = <0x00104000 0x1000>;
|
|
qcom,ipc = <&l2cc 0x8 2>;
|
|
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "ack", "err", "wakeup";
|
|
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
|
|
clock-names = "ram";
|
|
|
|
rpmcc: clock-controller {
|
|
compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
pm8901-regulators {
|
|
compatible = "qcom,rpm-pm8901-regulators";
|
|
|
|
pm8901_l0: l0 {};
|
|
pm8901_l1: l1 {};
|
|
pm8901_l2: l2 {};
|
|
pm8901_l3: l3 {};
|
|
pm8901_l4: l4 {};
|
|
pm8901_l5: l5 {};
|
|
pm8901_l6: l6 {};
|
|
|
|
/* S0 and S1 Handled as SAW regulators by SPM */
|
|
pm8901_s2: s2 {};
|
|
pm8901_s3: s3 {};
|
|
pm8901_s4: s4 {};
|
|
|
|
pm8901_lvs0: lvs0 {};
|
|
pm8901_lvs1: lvs1 {};
|
|
pm8901_lvs2: lvs2 {};
|
|
pm8901_lvs3: lvs3 {};
|
|
|
|
pm8901_mvs: mvs {};
|
|
};
|
|
|
|
pm8058-regulators {
|
|
compatible = "qcom,rpm-pm8058-regulators";
|
|
|
|
pm8058_l0: l0 {};
|
|
pm8058_l1: l1 {};
|
|
pm8058_l2: l2 {};
|
|
pm8058_l3: l3 {};
|
|
pm8058_l4: l4 {};
|
|
pm8058_l5: l5 {};
|
|
pm8058_l6: l6 {};
|
|
pm8058_l7: l7 {};
|
|
pm8058_l8: l8 {};
|
|
pm8058_l9: l9 {};
|
|
pm8058_l10: l10 {};
|
|
pm8058_l11: l11 {};
|
|
pm8058_l12: l12 {};
|
|
pm8058_l13: l13 {};
|
|
pm8058_l14: l14 {};
|
|
pm8058_l15: l15 {};
|
|
pm8058_l16: l16 {};
|
|
pm8058_l17: l17 {};
|
|
pm8058_l18: l18 {};
|
|
pm8058_l19: l19 {};
|
|
pm8058_l20: l20 {};
|
|
pm8058_l21: l21 {};
|
|
pm8058_l22: l22 {};
|
|
pm8058_l23: l23 {};
|
|
pm8058_l24: l24 {};
|
|
pm8058_l25: l25 {};
|
|
|
|
pm8058_s0: s0 {};
|
|
pm8058_s1: s1 {};
|
|
pm8058_s2: s2 {};
|
|
pm8058_s3: s3 {};
|
|
pm8058_s4: s4 {};
|
|
|
|
pm8058_lvs0: lvs0 {};
|
|
pm8058_lvs1: lvs1 {};
|
|
|
|
pm8058_ncp: ncp {};
|
|
};
|
|
};
|
|
|
|
amba {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
sdcc1: sdcc@12400000 {
|
|
status = "disabled";
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
reg = <0x12400000 0x8000>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cmd_irq";
|
|
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <8>;
|
|
max-frequency = <48000000>;
|
|
non-removable;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
};
|
|
|
|
sdcc3: sdcc@12180000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12180000 0x8000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cmd_irq";
|
|
clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <48000000>;
|
|
no-1-8-v;
|
|
};
|
|
|
|
sdcc5: sdcc@12200000 {
|
|
compatible = "arm,pl18x", "arm,primecell";
|
|
arm,primecell-periphid = <0x00051180>;
|
|
status = "disabled";
|
|
reg = <0x12200000 0x8000>;
|
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "cmd_irq";
|
|
clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
|
|
clock-names = "mclk", "apb_pclk";
|
|
bus-width = <4>;
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
max-frequency = <48000000>;
|
|
};
|
|
};
|
|
|
|
tcsr: syscon@1a400000 {
|
|
compatible = "qcom,tcsr-msm8660", "syscon";
|
|
reg = <0x1a400000 0x100>;
|
|
};
|
|
};
|
|
|
|
};
|