Paulo Zanoni 9adccc6063 drm/i915: add SW tracking to FBC enabling ... Currently, calling intel_fbc_enabled() will trigger a register read. And we call it a lot of times, even when FBC is disabled, so saving a few cycles would be a good thing. Another reason for this patch is because we currently call intel_fbc_enabled() while the HW is runtime suspended, so the read makes no sense and triggers a WARN. This happens even if FBC is disabled by default. Of course one could argue that we just shouldn't be calling intel_fbc_enabled() while the driver is runtime suspended, and I agree that's a good argument, but I still think that the reason explained in the first paragraph already justifies the patch. This problem can easily be reproduced with many subtests of igt/pm_rpm, and it is a regression introduced by: commit c5ad011d7d Author: Rodrigo Vivi <rodrigo.vivi@intel.com> Date: Mon Aug 4 03:51:38 2014 -0700 drm/i915: FBC flush nuke for BDW Testcase: igt/pm_rpm/cursor (and others) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2014-09-23 10:28:53 +02:00
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drm	drm/i915: add SW tracking to FBC enabling	2014-09-23 10:28:53 +02:00
host1x	drm/tegra: Make job submission 64-bit safe	2014-08-04 10:07:36 +02:00
ipu-v3	gpu: ipu-v3: Add ipu_dump()	2014-09-02 14:55:56 +02:00
vga	vgaarb: We can own non-decoded resources	2014-07-08 11:15:09 +10:00
Makefile	gpu: ipu-v3: Move i.MX IPUv3 core driver out of staging	2014-06-04 11:06:52 +02:00