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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0c3c8e1358
Some multipliers have a maximum rate that is lower than what the register width allows to. Add a field in the multiplier structure to allow CCU driver to set that maximum. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
163 lines
3.7 KiB
C
163 lines
3.7 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_nk.h"
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struct _ccu_nk {
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unsigned long n, min_n, max_n;
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unsigned long k, min_k, max_k;
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};
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static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
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struct _ccu_nk *nk)
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{
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unsigned long best_rate = 0;
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unsigned int best_k = 0, best_n = 0;
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unsigned int _k, _n;
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for (_k = nk->min_k; _k <= nk->max_k; _k++) {
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for (_n = nk->min_n; _n <= nk->max_n; _n++) {
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unsigned long tmp_rate = parent * _n * _k;
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if (tmp_rate > rate)
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continue;
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if ((rate - tmp_rate) < (rate - best_rate)) {
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best_rate = tmp_rate;
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best_k = _k;
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best_n = _n;
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}
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}
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}
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nk->k = best_k;
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nk->n = best_n;
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}
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static void ccu_nk_disable(struct clk_hw *hw)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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return ccu_gate_helper_disable(&nk->common, nk->enable);
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}
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static int ccu_nk_enable(struct clk_hw *hw)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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return ccu_gate_helper_enable(&nk->common, nk->enable);
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}
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static int ccu_nk_is_enabled(struct clk_hw *hw)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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return ccu_gate_helper_is_enabled(&nk->common, nk->enable);
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}
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static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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unsigned long rate, n, k;
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u32 reg;
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reg = readl(nk->common.base + nk->common.reg);
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n = reg >> nk->n.shift;
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n &= (1 << nk->n.width) - 1;
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n += nk->n.offset;
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if (!n)
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n++;
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k = reg >> nk->k.shift;
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k &= (1 << nk->k.width) - 1;
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k += nk->k.offset;
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if (!k)
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k++;
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rate = parent_rate * n * k;
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if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate /= nk->fixed_post_div;
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return rate;
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}
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static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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struct _ccu_nk _nk;
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if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate *= nk->fixed_post_div;
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_nk.min_n = nk->n.min;
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_nk.max_n = nk->n.max ?: 1 << nk->n.width;
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_nk.min_k = nk->k.min;
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_nk.max_k = nk->k.max ?: 1 << nk->k.width;
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ccu_nk_find_best(*parent_rate, rate, &_nk);
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rate = *parent_rate * _nk.n * _nk.k;
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if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate = rate / nk->fixed_post_div;
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return rate;
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}
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static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_nk *nk = hw_to_ccu_nk(hw);
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unsigned long flags;
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struct _ccu_nk _nk;
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u32 reg;
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if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV)
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rate = rate * nk->fixed_post_div;
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_nk.min_n = nk->n.min;
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_nk.max_n = nk->n.max ?: 1 << nk->n.width;
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_nk.min_k = nk->k.min;
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_nk.max_k = nk->k.max ?: 1 << nk->k.width;
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ccu_nk_find_best(parent_rate, rate, &_nk);
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spin_lock_irqsave(nk->common.lock, flags);
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reg = readl(nk->common.base + nk->common.reg);
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reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift);
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reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift);
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reg |= (_nk.k - nk->k.offset) << nk->k.shift;
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reg |= (_nk.n - nk->n.offset) << nk->n.shift;
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writel(reg, nk->common.base + nk->common.reg);
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spin_unlock_irqrestore(nk->common.lock, flags);
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ccu_helper_wait_for_lock(&nk->common, nk->lock);
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return 0;
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}
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const struct clk_ops ccu_nk_ops = {
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.disable = ccu_nk_disable,
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.enable = ccu_nk_enable,
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.is_enabled = ccu_nk_is_enabled,
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.recalc_rate = ccu_nk_recalc_rate,
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.round_rate = ccu_nk_round_rate,
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.set_rate = ccu_nk_set_rate,
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};
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