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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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97259e99bd
Move the different kinds of clocks into their own files. The reason is to aid readability of the code. This also goes along with the other SoC-specific clock drivers. The split introduces new structs for the three types of clocks and uses them. Other changes are not done to the code. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/*
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* Copyright 2011-2012 Calxeda, Inc.
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* Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Based from clk-highbank.c
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*
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include "clk.h"
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#define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw)
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static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
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unsigned long parent_rate)
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{
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struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk);
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u32 div;
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if (socfpgaclk->fixed_div)
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div = socfpgaclk->fixed_div;
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else
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div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
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return parent_rate / div;
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}
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static const struct clk_ops periclk_ops = {
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.recalc_rate = clk_periclk_recalc_rate,
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};
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static __init void __socfpga_periph_init(struct device_node *node,
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const struct clk_ops *ops)
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{
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u32 reg;
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struct clk *clk;
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struct socfpga_periph_clk *periph_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_init_data init;
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int rc;
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u32 fixed_div;
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of_property_read_u32(node, "reg", ®);
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periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL);
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if (WARN_ON(!periph_clk))
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return;
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periph_clk->hw.reg = clk_mgr_base_addr + reg;
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
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if (rc)
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periph_clk->fixed_div = 0;
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else
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periph_clk->fixed_div = fixed_div;
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of_property_read_string(node, "clock-output-names", &clk_name);
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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periph_clk->hw.hw.init = &init;
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clk = clk_register(NULL, &periph_clk->hw.hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(periph_clk);
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return;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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void __init socfpga_periph_init(struct device_node *node)
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{
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__socfpga_periph_init(node, &periclk_ops);
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}
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