Alex Frid 7157c69a99 clk: tegra: Fix Tegra210 PLLU initialization ... - Added necessary delays in PLLU enable sequence during initialization - Applied PLLU lock to all secondary gates (PLLU_48M and PLLU_60M were missing). Signed-off-by: Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2017-08-23 16:00:42 -07:00
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clk-audio-sync.c
clk-bpmp.c
clk-dfll.c
clk-dfll.h
clk-divider.c
clk-emc.c
clk-id.h
clk-periph-fixed.c
clk-periph-gate.c
clk-periph.c
clk-pll-out.c
clk-pll.c
clk-super.c
clk-tegra20.c
clk-tegra30.c
clk-tegra114.c
clk-tegra124-dfll-fcpu.c
clk-tegra124.c
clk-tegra210.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c
clk-tegra-pmc.c
clk-tegra-super-gen4.c
clk.c
clk.h
cvb.c
cvb.h
Kconfig
Makefile