mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-22 19:29:34 +07:00
9a9760dede
The following dt entries are added: cpus [0-3] (Cortex A53): - capacity-dmips-mhz = <592>; cpus [4-7] (Cortex A73): - capacity-dmips-mhz = <1024>; Those values were obtained by running dhrystone 2.1 on a HiKey960 with the following procedure: - Offline all CPUs but CPU0 (A53) - Set CPU0 frequency to maximum - Run Dhrystone 2.1 for 20 seconds - Offline all CPUs but CPU4 (A73) - set CPU4 frequency to maximum - Run Dhrystone 2.1 for 20 seconds The results are as follows: A53: 129633887 loops A73: 287034147 loops By scaling those values so that the A73s use 1024, we end up with 462 for the A53s. However, they have different maximum frequencies: 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 value to truly represent dmips per MHz, and we end up with 592. The impact of this change can be verified on HiKey960: $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq 1844000 1844000 1844000 1844000 2362000 2362000 2362000 2362000 $ cat /sys/devices/system/cpu/cpu*/cpu_capacity 462 462 462 462 1024 1024 1024 1024 Signed-off-by: Valentin Schneider <valentin.schneider@arm.com> Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> |
||
|---|---|---|
| .. | ||
| hi3660-hikey960.dts | ||
| hi3660.dtsi | ||
| hi3798cv200-poplar.dts | ||
| hi3798cv200.dtsi | ||
| hi6220-coresight.dtsi | ||
| hi6220-hikey.dts | ||
| hi6220.dtsi | ||
| hikey960-pinctrl.dtsi | ||
| hikey-pinctrl.dtsi | ||
| hip05-d02.dts | ||
| hip05.dtsi | ||
| hip06-d03.dts | ||
| hip06.dtsi | ||
| hip07-d05.dts | ||
| hip07.dtsi | ||
| Makefile | ||