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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8bed5a5cfc
The previous version made it necessary to first generate an EDID data set without correct CRC and then to fix the CRC in a second step. This patch adds the CRC calculation to the makefile in such a way that a correct EDID data set is generated in a single build step. Successfully tested with all existing and a couple of new data sets. Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.de> Reviewed-by: Carsten Emde <C.Emde@osadl.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
44 lines
1.2 KiB
ArmAsm
44 lines
1.2 KiB
ArmAsm
/*
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1600x1200.S: EDID data set for standard 1600x1200 60 Hz monitor
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Copyright (C) 2013 Carsten Emde <C.Emde@osadl.org>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/* EDID */
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#define VERSION 1
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#define REVISION 3
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/* Display */
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#define CLOCK 162000 /* kHz */
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#define XPIX 1600
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#define YPIX 1200
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#define XY_RATIO XY_RATIO_4_3
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#define XBLANK 560
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#define YBLANK 50
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#define XOFFSET 64
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#define XPULSE 192
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#define YOFFSET 1
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#define YPULSE 3
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#define DPI 72
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#define VFREQ 60 /* Hz */
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#define TIMING_NAME "Linux UXGA"
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/* No ESTABLISHED_TIMINGx_BITS */
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#define HSYNC_POL 1
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#define VSYNC_POL 1
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#include "edid.S"
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